Intel Corporation pet_reconstruction_ip intel_ai_ip_0 0.6 dla_clk clk dla_clk clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name ddr_clk clk ddr_clk clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name irq_clk clk irq_clk clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name dla_resetn reset_n dla_resetn associatedClock Associated clock dla_clk synchronousEdges Synchronous edges DEASSERT csr_axi awaddr csr_axi_awaddr awvalid csr_axi_awvalid awready csr_axi_awready wdata csr_axi_wdata wready csr_axi_wready wvalid csr_axi_wvalid wstrb csr_axi_wstrb bresp csr_axi_bresp bvalid csr_axi_bvalid bready csr_axi_bready rdata csr_axi_rdata rresp csr_axi_rresp rvalid csr_axi_rvalid rready csr_axi_rready araddr csr_axi_araddr arvalid csr_axi_arvalid arready csr_axi_arready awprot csr_axi_awprot arprot csr_axi_arprot associatedClock Associated clock ddr_clk associatedReset Associated reset dla_resetn trustzoneAware trustzoneAware true wakeupSignals wakeupSignals false uniqueIdSupport uniqueIdSupport false poison poison false traceSignals traceSignals false maximumOutstandingReads maximumOutstandingReads 1 maximumOutstandingWrites maximumOutstandingWrites 1 maximumOutstandingTransactions maximumOutstandingTransactions 1 dataCheck dataCheck false addressCheck addressCheck false securityAttribute securityAttribute false userData userData false readAcceptanceCapability Read acceptance capability 1 writeAcceptanceCapability Write acceptance capability 1 combinedAcceptanceCapability Combined acceptance capability 1 readDataReorderingDepth Read data reordering depth 1 bridgesToMaster bridgesToMaster dfhFeatureGuid Feature GUID 0 dfhGroupId Group ID 0 dfhParameterId ID dfhParameterName Name dfhParameterVersion Version dfhParameterData Data (HEX/DEC) dfhParameterDataLength Data length dfhFeatureMajorVersion Feature major version 0 dfhFeatureMinorVersion Feature minor version 0 dfhFeatureId Feature ID 35 dfhFeatureType Feature Type 3 ddr_axi awvalid ddr_axi_awvalid awprot ddr_axi_awprot awlen ddr_axi_awlen awready ddr_axi_awready awsize ddr_axi_awsize awburst ddr_axi_awburst arvalid ddr_axi_arvalid arprot ddr_axi_arprot arlen ddr_axi_arlen arready ddr_axi_arready arsize ddr_axi_arsize arburst ddr_axi_arburst rvalid ddr_axi_rvalid rready ddr_axi_rready wvalid ddr_axi_wvalid wlast ddr_axi_wlast wready ddr_axi_wready bvalid ddr_axi_bvalid bready ddr_axi_bready awaddr ddr_axi_awaddr awid ddr_axi_awid araddr ddr_axi_araddr arid ddr_axi_arid rdata ddr_axi_rdata rid ddr_axi_rid wdata ddr_axi_wdata wstrb ddr_axi_wstrb bid ddr_axi_bid associatedClock Associated clock ddr_clk associatedReset Associated reset dla_resetn trustzoneAware TrustZone-aware true wakeupSignals wakeupSignals false uniqueIdSupport uniqueIdSupport false poison poison false traceSignals traceSignals false maximumOutstandingReads maximumOutstandingReads 1 maximumOutstandingWrites maximumOutstandingWrites 1 maximumOutstandingTransactions maximumOutstandingTransactions 1 dataCheck dataCheck false addressCheck addressCheck false securityAttribute securityAttribute false userData userData false readIssuingCapability Read issuing capability 16 writeIssuingCapability Write issuing capability 16 combinedIssuingCapability Combined issuing capability 16 enableConcurrentSubordinateAccess enableConcurrentSubordinateAccess 0 noRepeatedIdsBetweenSubordinates noRepeatedIdsBetweenSubordinates 0 issuesINCRBursts Issues INCR bursts true issuesWRAPBursts Issues WRAP bursts false issuesFIXEDBursts Issues FIXED bursts false irq_level irq irq_level associatedAddressablePoint Associated addressable interface pet_reconstruction_ip.csr_axi associatedClock Associated clock irq_clk associatedReset Associated reset bridgedReceiverOffset Bridged receiver offset 0 bridgesToReceiver Bridges to receiver irqScheme Interrupt scheme INDIVIDUAL_REQUESTS QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH intel_ai_ip QUARTUS_SYNTH dla_clk in STD_LOGIC QUARTUS_SYNTH ddr_clk in STD_LOGIC QUARTUS_SYNTH irq_clk in STD_LOGIC QUARTUS_SYNTH dla_resetn in STD_LOGIC QUARTUS_SYNTH csr_axi_awaddr in 0 10 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_awvalid in STD_LOGIC QUARTUS_SYNTH csr_axi_awready out STD_LOGIC QUARTUS_SYNTH csr_axi_wdata in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_wready out STD_LOGIC QUARTUS_SYNTH csr_axi_wvalid in STD_LOGIC QUARTUS_SYNTH csr_axi_wstrb in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_bresp out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_bvalid out STD_LOGIC QUARTUS_SYNTH csr_axi_bready in STD_LOGIC QUARTUS_SYNTH csr_axi_rdata out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_rresp out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_rvalid out STD_LOGIC QUARTUS_SYNTH csr_axi_rready in STD_LOGIC QUARTUS_SYNTH csr_axi_araddr in 0 10 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_arvalid in STD_LOGIC QUARTUS_SYNTH csr_axi_arready out STD_LOGIC QUARTUS_SYNTH csr_axi_awprot in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH csr_axi_arprot in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_awvalid out STD_LOGIC QUARTUS_SYNTH ddr_axi_awprot out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_awlen out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_awready in STD_LOGIC QUARTUS_SYNTH ddr_axi_awsize out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_awburst out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_arvalid out STD_LOGIC QUARTUS_SYNTH ddr_axi_arprot out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_arlen out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_arready in STD_LOGIC QUARTUS_SYNTH ddr_axi_arsize out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_arburst out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_rvalid in STD_LOGIC QUARTUS_SYNTH ddr_axi_rready out STD_LOGIC QUARTUS_SYNTH ddr_axi_wvalid out STD_LOGIC QUARTUS_SYNTH ddr_axi_wlast out STD_LOGIC QUARTUS_SYNTH ddr_axi_wready in STD_LOGIC QUARTUS_SYNTH ddr_axi_bvalid in STD_LOGIC QUARTUS_SYNTH ddr_axi_bready out STD_LOGIC QUARTUS_SYNTH ddr_axi_awaddr out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_awid out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_araddr out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_arid out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_rdata in 0 511 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_rid in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_wdata out 0 511 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_wstrb out 0 63 STD_LOGIC_VECTOR QUARTUS_SYNTH ddr_axi_bid in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH irq_level out STD_LOGIC QUARTUS_SYNTH Intel Corporation pet_reconstruction_ip intel_ai_ip 0.6 ARCH_OPTION Architecture de5a_area_A10 device_family device_family Arria 10 CAP_ENABLED_INI CAP_ENABLED_INI false C_OMNI_CAP_TYPE Type 949 C_OMNI_CAP_VERSION Version 1 C_OMNI_CAP_SIZE Size (32bit Words) 2048 C_OMNI_CAP_ID_ASSOCIATED Associated ID 0 C_OMNI_CAP_ID_COMPONENT Component ID 0 C_OMNI_CAP_IRQ IRQ Vector (255:disabled) 255 C_OMNI_CAP_TAG Tag 0 C_OMNI_CAP_IRQ_ENABLE_EN IRQ Enable Exists 0 C_OMNI_CAP_IRQ_ENABLE IRQ Enable Register 0 C_OMNI_CAP_IRQ_STATUS_EN IRQ Status Exists 0 C_OMNI_CAP_IRQ_STATUS IRQ Status Register 0 board Board default device Device 10AX115N2F45E1SG deviceFamily Device family Arria 10 deviceSpeedGrade Device Speed Grade 1 generationId Generation Id 0 bonusData bonusData bonusData { element intel_ai_ip_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> dflBitArray dflBitArray cpuInfo cpuInfo false false