component pet_reconstruction_ip is port ( dla_clk : in std_logic := 'X'; -- clk ddr_clk : in std_logic := 'X'; -- clk irq_clk : in std_logic := 'X'; -- clk dla_resetn : in std_logic := 'X'; -- reset_n csr_axi_awaddr : in std_logic_vector(10 downto 0) := (others => 'X'); -- awaddr csr_axi_awvalid : in std_logic := 'X'; -- awvalid csr_axi_awready : out std_logic; -- awready csr_axi_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata csr_axi_wready : out std_logic; -- wready csr_axi_wvalid : in std_logic := 'X'; -- wvalid csr_axi_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb csr_axi_bresp : out std_logic_vector(1 downto 0); -- bresp csr_axi_bvalid : out std_logic; -- bvalid csr_axi_bready : in std_logic := 'X'; -- bready csr_axi_rdata : out std_logic_vector(31 downto 0); -- rdata csr_axi_rresp : out std_logic_vector(1 downto 0); -- rresp csr_axi_rvalid : out std_logic; -- rvalid csr_axi_rready : in std_logic := 'X'; -- rready csr_axi_araddr : in std_logic_vector(10 downto 0) := (others => 'X'); -- araddr csr_axi_arvalid : in std_logic := 'X'; -- arvalid csr_axi_arready : out std_logic; -- arready csr_axi_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot csr_axi_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot ddr_axi_awvalid : out std_logic; -- awvalid ddr_axi_awprot : out std_logic_vector(2 downto 0); -- awprot ddr_axi_awlen : out std_logic_vector(7 downto 0); -- awlen ddr_axi_awready : in std_logic := 'X'; -- awready ddr_axi_awsize : out std_logic_vector(2 downto 0); -- awsize ddr_axi_awburst : out std_logic_vector(1 downto 0); -- awburst ddr_axi_arvalid : out std_logic; -- arvalid ddr_axi_arprot : out std_logic_vector(2 downto 0); -- arprot ddr_axi_arlen : out std_logic_vector(7 downto 0); -- arlen ddr_axi_arready : in std_logic := 'X'; -- arready ddr_axi_arsize : out std_logic_vector(2 downto 0); -- arsize ddr_axi_arburst : out std_logic_vector(1 downto 0); -- arburst ddr_axi_rvalid : in std_logic := 'X'; -- rvalid ddr_axi_rready : out std_logic; -- rready ddr_axi_wvalid : out std_logic; -- wvalid ddr_axi_wlast : out std_logic; -- wlast ddr_axi_wready : in std_logic := 'X'; -- wready ddr_axi_bvalid : in std_logic := 'X'; -- bvalid ddr_axi_bready : out std_logic; -- bready ddr_axi_awaddr : out std_logic_vector(31 downto 0); -- awaddr ddr_axi_awid : out std_logic_vector(1 downto 0); -- awid ddr_axi_araddr : out std_logic_vector(31 downto 0); -- araddr ddr_axi_arid : out std_logic_vector(1 downto 0); -- arid ddr_axi_rdata : in std_logic_vector(511 downto 0) := (others => 'X'); -- rdata ddr_axi_rid : in std_logic_vector(1 downto 0) := (others => 'X'); -- rid ddr_axi_wdata : out std_logic_vector(511 downto 0); -- wdata ddr_axi_wstrb : out std_logic_vector(63 downto 0); -- wstrb ddr_axi_bid : in std_logic_vector(1 downto 0) := (others => 'X'); -- bid irq_level : out std_logic -- irq ); end component pet_reconstruction_ip;