set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_TOOL_VERSION "24.3"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_TOP_LEVEL_COMPONENT_NAME "intel_ai_ip"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name PRE_COMPILED_MODULE "ON"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name OCS_IP_FILE [file join $::quartus(qip_path) "../pet_reconstruction_ip.ip"]
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name OCS_IP_TYPE "intel_ai_ip"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name OCS_IP_VERSION "0.6"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name OCS_IP_HASH "d4v2tra"
set_global_assignment -library "pet_reconstruction_ip" -name SOPCINFO_FILE [file join $::quartus(qip_path) "pet_reconstruction_ip.sopcinfo"]
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name SLD_INFO "QSYS_NAME pet_reconstruction_ip HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "pet_reconstruction_ip" -name MISC_FILE [file join $::quartus(qip_path) "pet_reconstruction_ip.cmp"]
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pet_reconstruction_ip" -name MISC_FILE [file join $::quartus(qip_path) "../pet_reconstruction_ip.ip"]

set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_NAME "aW50ZWxfYWlfaXA="
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_DISPLAY_NAME "SW50ZWwgRlBHQSBBSSBTdWl0ZQ=="
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_VERSION "MC42"
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_COMPONENT_DESCRIPTION "VGhlIEludGVsIEZQR0EgQUkgU3VpdGUgaXMgYW4gQUkgRW5naW5lLg=="
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_COMPONENT_NAME "cGV0X3JlY29uc3RydWN0aW9uX2lw"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "pet_reconstruction_ip" -library "pet_reconstruction_ip" -name IP_COMPONENT_VERSION "MS4w"


set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/intel_ai_ip.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_altera_syncram_wrapped.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_ecc_encoder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_ecc_decoder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_dcfifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_reset_handler.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_reset_handler_simple.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_round_clamp.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_input_buffer_pipeline_stage.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_input_buffer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_core.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_debug.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_param_cache.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_lane.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_prelu.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_config_decoder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_mult_dsp.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_continuous_activations.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_clamp.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_group.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_control.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_S10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_A10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_AGX.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_C10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_control.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_pipeline_stage.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_input_buffer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_core.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_config_decoder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_debug.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_tree.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_group.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_lane.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult_fp16_chain_add.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_core.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_lane.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_config_decoder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult_fp16_adder_tree.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_group.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_control.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_fp32_convert.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_filter_bias_cache.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_s10_adder_tree.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_input_buffer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_pipeline_stage.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult_fp16.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_shift_register.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_fp16_mult_sum.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_debug.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_lane.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_exponent_wrapper.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_division_wrapper.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_control.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_debug.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_config_decoder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_group.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_pipeline_stage.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_core.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_input_buffer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_division_A10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_division_AGX.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_exponent_S10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_division_C10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_exponent_C10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_exponent_A10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_division_S10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_exponent_AGX.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_cdc_reset_sync.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_cdc_reset_async.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_clock_cross_full_sync_internal.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_clock_cross_half_sync_internal.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_clock_cross_half_sync.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_cdc_reset_aligned.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_clock_cross_full_sync.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_dspba_delay_ver.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_float_32_to_float_16.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_float_16_to_float_32.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_config_deserialize.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_fp32_mult_add.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_fp32_from_fpx_convert.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_prime_tensor_dot_sidefeed.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_prime_tensor_accumulation.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_value_counter.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_m18x18_full.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_fp32_mult_acc.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_fp32_add_sub.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_delay.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_timer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_ram.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_common_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_counter.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_latency_alignment.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dsp_m9x9_sumof4.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_bitscan_optimized.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_fp32_to_fpx_convert.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_ecc_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_ddrfree_config_data_read.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_config_network.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_config_data_split.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_config_data_concat.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_debug_network_node.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_debug_network.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_output_logic.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_mux.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_data_conversion.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_step_counter.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_ram_arb.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_dimension_counter.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_gen_index_info.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_funnel.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_layout_transform.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_lt_memory_manager.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_streamer_fsm.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_streamer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_output_streamer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_output_streamer_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_output_streamer_flush_handler.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_addr_gen.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_writer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_csr.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_reader.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_read_arb.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_config_intercept.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_counter_64.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_demux_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_demux.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_filter_bias_scale_scratchpad_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_filter_bias_scale_scratchpad.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_mid_speed_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_fanout_pipeline.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_lfsr.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_fifo_zero_width.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_low_latency_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_tessellated_incr_decr_threshold.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_latency_one_ram_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_std_synchronizer_nocut.v"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_zero_latency_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_latency_zero_ram_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_high_speed_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_tessellated_incr_lookahead.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_word_coalescer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_read_data_alignment.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_global_load_store.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_burst_coalescer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_read_cache.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_shift_register_no_reset.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_write_data_alignment.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_burst_splitter.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_unaligned_controller.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_coalescer_dynamic_timeout.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_data_aligner.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_lsu_write_kernel_downstream.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_generic_three_way_depth_stitch.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_tall_depth_stitch.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_short_depth_stitch.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_generic_two_way_depth_stitch.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_lower_mlab_simple_dual_port.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_bits_per_enable.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_lower_m20k_simple_dual_port.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_bottom_depth_stitch.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_remaining_width.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_bottom_width_stitch.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_lower_m20k_true_dual_port.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_ecc.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_hld_ram_lower.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_writer_config.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_reader_config.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_coord_validate_dim.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_manager.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_ram.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_fp_conversion.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_input_mux.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_reader_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_coord_gen.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_data_split.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_fp_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_coord_validate.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_addr_offset_gen.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_addr_gen_pipeline.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_max_value.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_top.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_block_align_mantissa.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_reader_addr_gen.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_stream_buffer_writer_addr_gen.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_interface_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_interface_profiling_counters.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack2x2_mult6x4.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_convert_alm.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack2x1_mult7.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult9_chain_add.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_signmag_to_2scomplement.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_blockfp_dsp.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_a10_c10_adder_tree.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_adder_tree.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_tensor_block_dot_and_convert.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_fp32_dsp.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult9_adder_tree.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_fp32_convert.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_convert_dsp.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_alm_s10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack2x2_mult5.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_sm_alm_s10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult9.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_blockfp_alm.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_s10_adder2.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_and_convert.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_accum_fixed.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_drain.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_blockfp_to_accum_input.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack1x1_mult18.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_alm.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack2x2_mult4.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_a10_adder1.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_2s_alm_s10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_c10_adder1.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_s10_adder1.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_2scomplement_to_signmag.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack2x2_mult5x4.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_tensor1x2_mult10_hidden_sideload.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_dsp_pack2x2_mult7.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_alm_a10_c10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dot_checker.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_alm_pipelined_accum.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_exit_fifo_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_sfc_backpressure_generator.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_exit_fifo.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_filter_ddr_unpack.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_sequencer_pe_control.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_sequencer_result_id_counters.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_sequencer_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_sequencer_scratchpad_control.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_sequencer.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_platform_reset.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_platform_reset_internal.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_top_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_width_adapter.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_width_adapter_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_xbar_config_handler.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_xbar_pkg.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_xbar_wrapper.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_xbar.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_st_pipeline_stage.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_pool_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_depthwise_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_softmax_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_layout_transform_config.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_filter_bias_scale_scratchpad_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_interface_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_xbar_if.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000116_invTables_lutmem.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000119_invTables_lutmem.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0001ock_rsrvd_fix_lutmem.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0002ock_rsrvd_fix_lutmem.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0000ock_rsrvd_fix_lutmem.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000113_invTables_lutmem.mif"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_width_clip.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_functions.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_activation_constants.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_vector_dot_arch_info.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_common_types.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_constants.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_common_macros.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_generic_pkg.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_aux_generic_debug_pkg.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_acl_parameter_assert.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_common_enums.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_layout_transform_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_output_streamer_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_config_filter_reader.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_config_feature_reader.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_config_feature_writer.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_config_reader.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_constants.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_demux_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_filter_bias_scale_scratchpad_arch_info.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_constants.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_out_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_writer_mux_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_sb_xbar_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_reader_config_vc.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_in_config.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_input_feeder_writer_config_vc.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array_constants.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array_enums.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array_arch_t.svh"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_top_derived_params.svh"]
set_global_assignment -library "intel_ai_ip_06" -name SDC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_clock_cross_sync.sdc"]
set_global_assignment -library "intel_ai_ip_06" -name MISC_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_param.svh"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_dma_csr_discovery_rom.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SOURCE_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_interface_profiling_counters.mif"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_pe_array_system_de5a_area_A10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_top_de5a_area_A10.sv"]
set_global_assignment -library "intel_ai_ip_06" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_ai_ip_06/synth/intel_ai_ip/dla_top_wrapper_de5a_area_A10.sv"]
set_global_assignment -library "pet_reconstruction_ip" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/pet_reconstruction_ip.v"]


set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_TOOL_NAME "intel_ai_ip"
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_TOOL_VERSION "0.6"
set_global_assignment -entity "intel_ai_ip" -library "intel_ai_ip_06" -name IP_TOOL_ENV "QsysPrimePro"