# -------------------------------------------------------------------------- # # # Copyright (C) 2024 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the Intel FPGA Software License Subscription Agreements # on the Quartus Prime software download page. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 24.3.0 Build 212 11/18/2024 SC Pro Edition # Date created = 11:10:31 January 23, 2025 # # -------------------------------------------------------------------------- # set_global_assignment -name TOP_LEVEL_ENTITY pet_reconstruction set_global_assignment -name ORIGINAL_QUARTUS_VERSION 24.3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:10:31 JANUARY 23, 2025" set_global_assignment -name LAST_QUARTUS_VERSION "24.3.0 Pro Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 set_global_assignment -name DEVICE 10AX115N2F45E1SG set_global_assignment -name FAMILY "Arria 10" set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name IP_FILE ip/pet_reconstruction_ip.ip set_global_assignment -name BOARD default