ura/%2525253fid%2525253d79a0ea11dcb4bf5135259532524318bc750608d2%25253fid%25253d7bcd492df9179d271896b4fa8071a324607a88cd%253fid%253d0f7acbddf97ce93a07cd46fdbe81cb0208c7e5c0%3fid%3d0f7acbddf97ce93a07cd46fdbe81cb0208c7e5c0&id2%3da51bde729f6885967b1a4d3d72c0c7b7576273e0?h=master, branch masterSVM Implementation in Python, C and Verilog