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| author | Eric Dao <eric@erickhangdao.com> | 2025-03-10 17:54:31 -0400 |
|---|---|---|
| committer | Eric Dao <eric@erickhangdao.com> | 2025-03-10 17:54:31 -0400 |
| commit | ab224e2e6ba65f5a369ec392f99cd8845ad06c98 (patch) | |
| tree | a1e757e9341863ed52b8ad4c5a1c45933aab9da4 /python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_config.svh | |
| parent | 40da1752f2c8639186b72f6838aa415e854d0b1d (diff) | |
| download | thesis-master.tar.gz thesis-master.tar.bz2 thesis-master.zip | |
Diffstat (limited to 'python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_config.svh')
| -rw-r--r-- | python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_config.svh | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_config.svh b/python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_config.svh new file mode 100644 index 0000000..d21048a --- /dev/null +++ b/python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_config.svh @@ -0,0 +1,30 @@ +// Copyright 2024 Intel Corporation. +// +// This software and the related documents are Intel copyrighted materials, +// and your use of them is governed by the express license under which they +// were provided to you ("License"). Unless the License provides otherwise, +// you may not use, modify, copy, publish, distribute, disclose or transmit +// this software or the related documents without Intel's prior written +// permission. +// +// This software and the related documents are provided as is, with no express +// or implied warranties, other than those that are expressly stated in the +// License. + +/* + This is the shared datatype between C++ compiler config generation and output streamer RTL +*/ +typedef struct packed { + uint32_t valid_bytes_stream_width; // number of valid bytes for last transfer of one HW pixel, used to drive the tstrb signal + uint16_t transfers_per_hw_pixel; // total number of AXI transfers for one pixel in HW (all output channels of one pixel) + uint32_t total_transfers; // total number of AXI transfers for a layer given the AXI data width + uint32_t total_transfers_adjusted; // total number of AXI transfers for a layer minus the last invalid transactions if any + uint8_t last_index; // index of transaction within a single HW pixel where some valid and invalid elements exist + uint8_t last_stream; // bool to determine if this is the last stream to generate the tlast signal (mainly for multi-output support) +} output_streamer_config_t; + +typedef struct packed { + uint32_t total_transfers; // total number of input transactions from xbar to output streamer width adapter + uint32_t transfers_per_hw_pixel; // total number of xbar transfers for one pixel in HW (all output channels of one pixel) + uint32_t flush_index; // index of the last transaction at a given pixel, where we need to flush the width adapter and move to next pixel +} output_streamer_flush_config_t; |
