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| author | Eric Dao <eric@erickhangdao.com> | 2025-03-10 17:54:31 -0400 |
|---|---|---|
| committer | Eric Dao <eric@erickhangdao.com> | 2025-03-10 17:54:31 -0400 |
| commit | ab224e2e6ba65f5a369ec392f99cd8845ad06c98 (patch) | |
| tree | a1e757e9341863ed52b8ad4c5a1c45933aab9da4 /python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_bb.v | |
| parent | 40da1752f2c8639186b72f6838aa415e854d0b1d (diff) | |
| download | thesis-master.tar.gz thesis-master.tar.bz2 thesis-master.zip | |
Diffstat (limited to 'python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_bb.v')
| -rw-r--r-- | python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_bb.v | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_bb.v b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_bb.v new file mode 100644 index 0000000..c96d3ad --- /dev/null +++ b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_bb.v @@ -0,0 +1,56 @@ +module pet_reconstruction_ip ( + input wire dla_clk, // dla_clk.clk + input wire ddr_clk, // ddr_clk.clk + input wire irq_clk, // irq_clk.clk + input wire dla_resetn, // dla_resetn.reset_n + input wire [10:0] csr_axi_awaddr, // csr_axi.awaddr + input wire csr_axi_awvalid, // .awvalid + output wire csr_axi_awready, // .awready + input wire [31:0] csr_axi_wdata, // .wdata + output wire csr_axi_wready, // .wready + input wire csr_axi_wvalid, // .wvalid + input wire [3:0] csr_axi_wstrb, // .wstrb + output wire [1:0] csr_axi_bresp, // .bresp + output wire csr_axi_bvalid, // .bvalid + input wire csr_axi_bready, // .bready + output wire [31:0] csr_axi_rdata, // .rdata + output wire [1:0] csr_axi_rresp, // .rresp + output wire csr_axi_rvalid, // .rvalid + input wire csr_axi_rready, // .rready + input wire [10:0] csr_axi_araddr, // .araddr + input wire csr_axi_arvalid, // .arvalid + output wire csr_axi_arready, // .arready + input wire [2:0] csr_axi_awprot, // .awprot + input wire [2:0] csr_axi_arprot, // .arprot + output wire ddr_axi_awvalid, // ddr_axi.awvalid + output wire [2:0] ddr_axi_awprot, // .awprot + output wire [7:0] ddr_axi_awlen, // .awlen + input wire ddr_axi_awready, // .awready + output wire [2:0] ddr_axi_awsize, // .awsize + output wire [1:0] ddr_axi_awburst, // .awburst + output wire ddr_axi_arvalid, // .arvalid + output wire [2:0] ddr_axi_arprot, // .arprot + output wire [7:0] ddr_axi_arlen, // .arlen + input wire ddr_axi_arready, // .arready + output wire [2:0] ddr_axi_arsize, // .arsize + output wire [1:0] ddr_axi_arburst, // .arburst + input wire ddr_axi_rvalid, // .rvalid + output wire ddr_axi_rready, // .rready + output wire ddr_axi_wvalid, // .wvalid + output wire ddr_axi_wlast, // .wlast + input wire ddr_axi_wready, // .wready + input wire ddr_axi_bvalid, // .bvalid + output wire ddr_axi_bready, // .bready + output wire [31:0] ddr_axi_awaddr, // .awaddr + output wire [1:0] ddr_axi_awid, // .awid + output wire [31:0] ddr_axi_araddr, // .araddr + output wire [1:0] ddr_axi_arid, // .arid + input wire [511:0] ddr_axi_rdata, // .rdata + input wire [1:0] ddr_axi_rid, // .rid + output wire [511:0] ddr_axi_wdata, // .wdata + output wire [63:0] ddr_axi_wstrb, // .wstrb + input wire [1:0] ddr_axi_bid, // .bid + output wire irq_level // irq_level.irq + ); +endmodule + |