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| author | Eric Dao <eric@erickhangdao.com> | 2025-03-10 17:54:31 -0400 |
|---|---|---|
| committer | Eric Dao <eric@erickhangdao.com> | 2025-03-10 17:54:31 -0400 |
| commit | ab224e2e6ba65f5a369ec392f99cd8845ad06c98 (patch) | |
| tree | a1e757e9341863ed52b8ad4c5a1c45933aab9da4 /python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.vhd | |
| parent | 40da1752f2c8639186b72f6838aa415e854d0b1d (diff) | |
| download | thesis-master.tar.gz thesis-master.tar.bz2 thesis-master.zip | |
Diffstat (limited to 'python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.vhd')
| -rw-r--r-- | python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.vhd | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.vhd b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.vhd new file mode 100644 index 0000000..03c8017 --- /dev/null +++ b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.vhd @@ -0,0 +1,113 @@ + component pet_reconstruction_ip is + port ( + dla_clk : in std_logic := 'X'; -- clk + ddr_clk : in std_logic := 'X'; -- clk + irq_clk : in std_logic := 'X'; -- clk + dla_resetn : in std_logic := 'X'; -- reset_n + csr_axi_awaddr : in std_logic_vector(10 downto 0) := (others => 'X'); -- awaddr + csr_axi_awvalid : in std_logic := 'X'; -- awvalid + csr_axi_awready : out std_logic; -- awready + csr_axi_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata + csr_axi_wready : out std_logic; -- wready + csr_axi_wvalid : in std_logic := 'X'; -- wvalid + csr_axi_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb + csr_axi_bresp : out std_logic_vector(1 downto 0); -- bresp + csr_axi_bvalid : out std_logic; -- bvalid + csr_axi_bready : in std_logic := 'X'; -- bready + csr_axi_rdata : out std_logic_vector(31 downto 0); -- rdata + csr_axi_rresp : out std_logic_vector(1 downto 0); -- rresp + csr_axi_rvalid : out std_logic; -- rvalid + csr_axi_rready : in std_logic := 'X'; -- rready + csr_axi_araddr : in std_logic_vector(10 downto 0) := (others => 'X'); -- araddr + csr_axi_arvalid : in std_logic := 'X'; -- arvalid + csr_axi_arready : out std_logic; -- arready + csr_axi_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot + csr_axi_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot + ddr_axi_awvalid : out std_logic; -- awvalid + ddr_axi_awprot : out std_logic_vector(2 downto 0); -- awprot + ddr_axi_awlen : out std_logic_vector(7 downto 0); -- awlen + ddr_axi_awready : in std_logic := 'X'; -- awready + ddr_axi_awsize : out std_logic_vector(2 downto 0); -- awsize + ddr_axi_awburst : out std_logic_vector(1 downto 0); -- awburst + ddr_axi_arvalid : out std_logic; -- arvalid + ddr_axi_arprot : out std_logic_vector(2 downto 0); -- arprot + ddr_axi_arlen : out std_logic_vector(7 downto 0); -- arlen + ddr_axi_arready : in std_logic := 'X'; -- arready + ddr_axi_arsize : out std_logic_vector(2 downto 0); -- arsize + ddr_axi_arburst : out std_logic_vector(1 downto 0); -- arburst + ddr_axi_rvalid : in std_logic := 'X'; -- rvalid + ddr_axi_rready : out std_logic; -- rready + ddr_axi_wvalid : out std_logic; -- wvalid + ddr_axi_wlast : out std_logic; -- wlast + ddr_axi_wready : in std_logic := 'X'; -- wready + ddr_axi_bvalid : in std_logic := 'X'; -- bvalid + ddr_axi_bready : out std_logic; -- bready + ddr_axi_awaddr : out std_logic_vector(31 downto 0); -- awaddr + ddr_axi_awid : out std_logic_vector(1 downto 0); -- awid + ddr_axi_araddr : out std_logic_vector(31 downto 0); -- araddr + ddr_axi_arid : out std_logic_vector(1 downto 0); -- arid + ddr_axi_rdata : in std_logic_vector(511 downto 0) := (others => 'X'); -- rdata + ddr_axi_rid : in std_logic_vector(1 downto 0) := (others => 'X'); -- rid + ddr_axi_wdata : out std_logic_vector(511 downto 0); -- wdata + ddr_axi_wstrb : out std_logic_vector(63 downto 0); -- wstrb + ddr_axi_bid : in std_logic_vector(1 downto 0) := (others => 'X'); -- bid + irq_level : out std_logic -- irq + ); + end component pet_reconstruction_ip; + + u0 : component pet_reconstruction_ip + port map ( + dla_clk => CONNECTED_TO_dla_clk, -- dla_clk.clk + ddr_clk => CONNECTED_TO_ddr_clk, -- ddr_clk.clk + irq_clk => CONNECTED_TO_irq_clk, -- irq_clk.clk + dla_resetn => CONNECTED_TO_dla_resetn, -- dla_resetn.reset_n + csr_axi_awaddr => CONNECTED_TO_csr_axi_awaddr, -- csr_axi.awaddr + csr_axi_awvalid => CONNECTED_TO_csr_axi_awvalid, -- .awvalid + csr_axi_awready => CONNECTED_TO_csr_axi_awready, -- .awready + csr_axi_wdata => CONNECTED_TO_csr_axi_wdata, -- .wdata + csr_axi_wready => CONNECTED_TO_csr_axi_wready, -- .wready + csr_axi_wvalid => CONNECTED_TO_csr_axi_wvalid, -- .wvalid + csr_axi_wstrb => CONNECTED_TO_csr_axi_wstrb, -- .wstrb + csr_axi_bresp => CONNECTED_TO_csr_axi_bresp, -- .bresp + csr_axi_bvalid => CONNECTED_TO_csr_axi_bvalid, -- .bvalid + csr_axi_bready => CONNECTED_TO_csr_axi_bready, -- .bready + csr_axi_rdata => CONNECTED_TO_csr_axi_rdata, -- .rdata + csr_axi_rresp => CONNECTED_TO_csr_axi_rresp, -- .rresp + csr_axi_rvalid => CONNECTED_TO_csr_axi_rvalid, -- .rvalid + csr_axi_rready => CONNECTED_TO_csr_axi_rready, -- .rready + csr_axi_araddr => CONNECTED_TO_csr_axi_araddr, -- .araddr + csr_axi_arvalid => CONNECTED_TO_csr_axi_arvalid, -- .arvalid + csr_axi_arready => CONNECTED_TO_csr_axi_arready, -- .arready + csr_axi_awprot => CONNECTED_TO_csr_axi_awprot, -- .awprot + csr_axi_arprot => CONNECTED_TO_csr_axi_arprot, -- .arprot + ddr_axi_awvalid => CONNECTED_TO_ddr_axi_awvalid, -- ddr_axi.awvalid + ddr_axi_awprot => CONNECTED_TO_ddr_axi_awprot, -- .awprot + ddr_axi_awlen => CONNECTED_TO_ddr_axi_awlen, -- .awlen + ddr_axi_awready => CONNECTED_TO_ddr_axi_awready, -- .awready + ddr_axi_awsize => CONNECTED_TO_ddr_axi_awsize, -- .awsize + ddr_axi_awburst => CONNECTED_TO_ddr_axi_awburst, -- .awburst + ddr_axi_arvalid => CONNECTED_TO_ddr_axi_arvalid, -- .arvalid + ddr_axi_arprot => CONNECTED_TO_ddr_axi_arprot, -- .arprot + ddr_axi_arlen => CONNECTED_TO_ddr_axi_arlen, -- .arlen + ddr_axi_arready => CONNECTED_TO_ddr_axi_arready, -- .arready + ddr_axi_arsize => CONNECTED_TO_ddr_axi_arsize, -- .arsize + ddr_axi_arburst => CONNECTED_TO_ddr_axi_arburst, -- .arburst + ddr_axi_rvalid => CONNECTED_TO_ddr_axi_rvalid, -- .rvalid + ddr_axi_rready => CONNECTED_TO_ddr_axi_rready, -- .rready + ddr_axi_wvalid => CONNECTED_TO_ddr_axi_wvalid, -- .wvalid + ddr_axi_wlast => CONNECTED_TO_ddr_axi_wlast, -- .wlast + ddr_axi_wready => CONNECTED_TO_ddr_axi_wready, -- .wready + ddr_axi_bvalid => CONNECTED_TO_ddr_axi_bvalid, -- .bvalid + ddr_axi_bready => CONNECTED_TO_ddr_axi_bready, -- .bready + ddr_axi_awaddr => CONNECTED_TO_ddr_axi_awaddr, -- .awaddr + ddr_axi_awid => CONNECTED_TO_ddr_axi_awid, -- .awid + ddr_axi_araddr => CONNECTED_TO_ddr_axi_araddr, -- .araddr + ddr_axi_arid => CONNECTED_TO_ddr_axi_arid, -- .arid + ddr_axi_rdata => CONNECTED_TO_ddr_axi_rdata, -- .rdata + ddr_axi_rid => CONNECTED_TO_ddr_axi_rid, -- .rid + ddr_axi_wdata => CONNECTED_TO_ddr_axi_wdata, -- .wdata + ddr_axi_wstrb => CONNECTED_TO_ddr_axi_wstrb, -- .wstrb + ddr_axi_bid => CONNECTED_TO_ddr_axi_bid, -- .bid + irq_level => CONNECTED_TO_irq_level -- irq_level.irq + ); + |