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1 files changed, 123 insertions, 0 deletions

diff --git a/python/openvino/demo/quartus/ip/pet_reconstruction_ip/synth/pet_reconstruction_ip.v b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/synth/pet_reconstruction_ip.v
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+++ b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/synth/pet_reconstruction_ip.v
@@ -0,0 +1,123 @@
+// pet_reconstruction_ip.v
+
+// Generated using ACDS version 24.3 212
+
+`timescale 1 ps / 1 ps
+module pet_reconstruction_ip (
+		input  wire         dla_clk,         //    dla_clk.clk
+		input  wire         ddr_clk,         //    ddr_clk.clk
+		input  wire         irq_clk,         //    irq_clk.clk
+		input  wire         dla_resetn,      // dla_resetn.reset_n
+		input  wire [10:0]  csr_axi_awaddr,  //    csr_axi.awaddr
+		input  wire         csr_axi_awvalid, //           .awvalid
+		output wire         csr_axi_awready, //           .awready
+		input  wire [31:0]  csr_axi_wdata,   //           .wdata
+		output wire         csr_axi_wready,  //           .wready
+		input  wire         csr_axi_wvalid,  //           .wvalid
+		input  wire [3:0]   csr_axi_wstrb,   //           .wstrb
+		output wire [1:0]   csr_axi_bresp,   //           .bresp
+		output wire         csr_axi_bvalid,  //           .bvalid
+		input  wire         csr_axi_bready,  //           .bready
+		output wire [31:0]  csr_axi_rdata,   //           .rdata
+		output wire [1:0]   csr_axi_rresp,   //           .rresp
+		output wire         csr_axi_rvalid,  //           .rvalid
+		input  wire         csr_axi_rready,  //           .rready
+		input  wire [10:0]  csr_axi_araddr,  //           .araddr
+		input  wire         csr_axi_arvalid, //           .arvalid
+		output wire         csr_axi_arready, //           .arready
+		input  wire [2:0]   csr_axi_awprot,  //           .awprot
+		input  wire [2:0]   csr_axi_arprot,  //           .arprot
+		output wire         ddr_axi_awvalid, //    ddr_axi.awvalid
+		output wire [2:0]   ddr_axi_awprot,  //           .awprot
+		output wire [7:0]   ddr_axi_awlen,   //           .awlen
+		input  wire         ddr_axi_awready, //           .awready
+		output wire [2:0]   ddr_axi_awsize,  //           .awsize
+		output wire [1:0]   ddr_axi_awburst, //           .awburst
+		output wire         ddr_axi_arvalid, //           .arvalid
+		output wire [2:0]   ddr_axi_arprot,  //           .arprot
+		output wire [7:0]   ddr_axi_arlen,   //           .arlen
+		input  wire         ddr_axi_arready, //           .arready
+		output wire [2:0]   ddr_axi_arsize,  //           .arsize
+		output wire [1:0]   ddr_axi_arburst, //           .arburst
+		input  wire         ddr_axi_rvalid,  //           .rvalid
+		output wire         ddr_axi_rready,  //           .rready
+		output wire         ddr_axi_wvalid,  //           .wvalid
+		output wire         ddr_axi_wlast,   //           .wlast
+		input  wire         ddr_axi_wready,  //           .wready
+		input  wire         ddr_axi_bvalid,  //           .bvalid
+		output wire         ddr_axi_bready,  //           .bready
+		output wire [31:0]  ddr_axi_awaddr,  //           .awaddr
+		output wire [1:0]   ddr_axi_awid,    //           .awid
+		output wire [31:0]  ddr_axi_araddr,  //           .araddr
+		output wire [1:0]   ddr_axi_arid,    //           .arid
+		input  wire [511:0] ddr_axi_rdata,   //           .rdata
+		input  wire [1:0]   ddr_axi_rid,     //           .rid
+		output wire [511:0] ddr_axi_wdata,   //           .wdata
+		output wire [63:0]  ddr_axi_wstrb,   //           .wstrb
+		input  wire [1:0]   ddr_axi_bid,     //           .bid
+		output wire         irq_level        //  irq_level.irq
+	);
+
+	intel_ai_ip #(
+		.ARCH_OPTION               ("de5a_area_A10"),
+		.C_CSR_AXI_ADDR_WIDTH      (11),
+		.C_CSR_AXI_DATA_WIDTH      (32),
+		.C_DDR_AXI_ADDR_WIDTH      (32),
+		.C_DDR_AXI_DATA_WIDTH      (512),
+		.C_DDR_AXI_THREAD_ID_WIDTH (2)
+	) intel_ai_ip_0 (
+		.dla_clk         (dla_clk),         //   input,    width = 1,    dla_clk.clk
+		.ddr_clk         (ddr_clk),         //   input,    width = 1,    ddr_clk.clk
+		.irq_clk         (irq_clk),         //   input,    width = 1,    irq_clk.clk
+		.dla_resetn      (dla_resetn),      //   input,    width = 1, dla_resetn.reset_n
+		.csr_axi_awaddr  (csr_axi_awaddr),  //   input,   width = 11,    csr_axi.awaddr
+		.csr_axi_awvalid (csr_axi_awvalid), //   input,    width = 1,           .awvalid
+		.csr_axi_awready (csr_axi_awready), //  output,    width = 1,           .awready
+		.csr_axi_wdata   (csr_axi_wdata),   //   input,   width = 32,           .wdata
+		.csr_axi_wready  (csr_axi_wready),  //  output,    width = 1,           .wready
+		.csr_axi_wvalid  (csr_axi_wvalid),  //   input,    width = 1,           .wvalid
+		.csr_axi_wstrb   (csr_axi_wstrb),   //   input,    width = 4,           .wstrb
+		.csr_axi_bresp   (csr_axi_bresp),   //  output,    width = 2,           .bresp
+		.csr_axi_bvalid  (csr_axi_bvalid),  //  output,    width = 1,           .bvalid
+		.csr_axi_bready  (csr_axi_bready),  //   input,    width = 1,           .bready
+		.csr_axi_rdata   (csr_axi_rdata),   //  output,   width = 32,           .rdata
+		.csr_axi_rresp   (csr_axi_rresp),   //  output,    width = 2,           .rresp
+		.csr_axi_rvalid  (csr_axi_rvalid),  //  output,    width = 1,           .rvalid
+		.csr_axi_rready  (csr_axi_rready),  //   input,    width = 1,           .rready
+		.csr_axi_araddr  (csr_axi_araddr),  //   input,   width = 11,           .araddr
+		.csr_axi_arvalid (csr_axi_arvalid), //   input,    width = 1,           .arvalid
+		.csr_axi_arready (csr_axi_arready), //  output,    width = 1,           .arready
+		.csr_axi_awprot  (csr_axi_awprot),  //   input,    width = 3,           .awprot
+		.csr_axi_arprot  (csr_axi_arprot),  //   input,    width = 3,           .arprot
+		.ddr_axi_awvalid (ddr_axi_awvalid), //  output,    width = 1,    ddr_axi.awvalid
+		.ddr_axi_awprot  (ddr_axi_awprot),  //  output,    width = 3,           .awprot
+		.ddr_axi_awlen   (ddr_axi_awlen),   //  output,    width = 8,           .awlen
+		.ddr_axi_awready (ddr_axi_awready), //   input,    width = 1,           .awready
+		.ddr_axi_awsize  (ddr_axi_awsize),  //  output,    width = 3,           .awsize
+		.ddr_axi_awburst (ddr_axi_awburst), //  output,    width = 2,           .awburst
+		.ddr_axi_arvalid (ddr_axi_arvalid), //  output,    width = 1,           .arvalid
+		.ddr_axi_arprot  (ddr_axi_arprot),  //  output,    width = 3,           .arprot
+		.ddr_axi_arlen   (ddr_axi_arlen),   //  output,    width = 8,           .arlen
+		.ddr_axi_arready (ddr_axi_arready), //   input,    width = 1,           .arready
+		.ddr_axi_arsize  (ddr_axi_arsize),  //  output,    width = 3,           .arsize
+		.ddr_axi_arburst (ddr_axi_arburst), //  output,    width = 2,           .arburst
+		.ddr_axi_rvalid  (ddr_axi_rvalid),  //   input,    width = 1,           .rvalid
+		.ddr_axi_rready  (ddr_axi_rready),  //  output,    width = 1,           .rready
+		.ddr_axi_wvalid  (ddr_axi_wvalid),  //  output,    width = 1,           .wvalid
+		.ddr_axi_wlast   (ddr_axi_wlast),   //  output,    width = 1,           .wlast
+		.ddr_axi_wready  (ddr_axi_wready),  //   input,    width = 1,           .wready
+		.ddr_axi_bvalid  (ddr_axi_bvalid),  //   input,    width = 1,           .bvalid
+		.ddr_axi_bready  (ddr_axi_bready),  //  output,    width = 1,           .bready
+		.ddr_axi_awaddr  (ddr_axi_awaddr),  //  output,   width = 32,           .awaddr
+		.ddr_axi_awid    (ddr_axi_awid),    //  output,    width = 2,           .awid
+		.ddr_axi_araddr  (ddr_axi_araddr),  //  output,   width = 32,           .araddr
+		.ddr_axi_arid    (ddr_axi_arid),    //  output,    width = 2,           .arid
+		.ddr_axi_rdata   (ddr_axi_rdata),   //   input,  width = 512,           .rdata
+		.ddr_axi_rid     (ddr_axi_rid),     //   input,    width = 2,           .rid
+		.ddr_axi_wdata   (ddr_axi_wdata),   //  output,  width = 512,           .wdata
+		.ddr_axi_wstrb   (ddr_axi_wstrb),   //  output,   width = 64,           .wstrb
+		.ddr_axi_bid     (ddr_axi_bid),     //   input,    width = 2,           .bid
+		.irq_level       (irq_level)        //  output,    width = 1,  irq_level.irq
+	);
+
+endmodule