diff options
Diffstat (limited to 'python/openvino/demo/ip/intel_ai_ip/static_files.tcl')
| -rw-r--r-- | python/openvino/demo/ip/intel_ai_ip/static_files.tcl | 313 |
1 files changed, 313 insertions, 0 deletions
diff --git a/python/openvino/demo/ip/intel_ai_ip/static_files.tcl b/python/openvino/demo/ip/intel_ai_ip/static_files.tcl new file mode 100644 index 0000000..0fcfd46 --- /dev/null +++ b/python/openvino/demo/ip/intel_ai_ip/static_files.tcl @@ -0,0 +1,313 @@ +add_fileset_file intel_ai_ip/dla_acl_altera_syncram_wrapped.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_altera_syncram_wrapped.sv +add_fileset_file intel_ai_ip/dla_acl_ecc_encoder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_ecc_encoder.sv +add_fileset_file intel_ai_ip/dla_acl_ecc_decoder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_ecc_decoder.sv +add_fileset_file intel_ai_ip/dla_acl_dcfifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_dcfifo.sv +add_fileset_file intel_ai_ip/dla_acl_reset_handler.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_reset_handler.sv +add_fileset_file intel_ai_ip/dla_reset_handler_simple.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_reset_handler_simple.sv +add_fileset_file intel_ai_ip/dla_aux_activation_round_clamp.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_round_clamp.sv +add_fileset_file intel_ai_ip/dla_aux_activation_input_buffer_pipeline_stage.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_input_buffer_pipeline_stage.sv +add_fileset_file intel_ai_ip/dla_aux_activation_input_buffer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_input_buffer.sv +add_fileset_file intel_ai_ip/dla_aux_activation_core.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_core.sv +add_fileset_file intel_ai_ip/dla_aux_activation_debug.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_debug.sv +add_fileset_file intel_ai_ip/dla_aux_activation_param_cache.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_param_cache.sv +add_fileset_file intel_ai_ip/dla_aux_activation_lane.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_lane.sv +add_fileset_file intel_ai_ip/dla_aux_activation_prelu.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_prelu.sv +add_fileset_file intel_ai_ip/dla_aux_activation_config_decoder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_config_decoder.sv +add_fileset_file intel_ai_ip/dla_aux_activation_mult_dsp.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_mult_dsp.sv +add_fileset_file intel_ai_ip/dla_aux_activation_continuous_activations.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_continuous_activations.sv +add_fileset_file intel_ai_ip/dla_aux_activation_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_top.sv +add_fileset_file intel_ai_ip/dla_aux_activation_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_pkg.sv +add_fileset_file intel_ai_ip/dla_aux_activation_clamp.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_clamp.sv +add_fileset_file intel_ai_ip/dla_aux_activation_group.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_group.sv +add_fileset_file intel_ai_ip/dla_aux_activation_control.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_control.sv +add_fileset_file intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_S10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_sigmoid_tanh_recip_half_S10.sv +add_fileset_file intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_A10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_sigmoid_tanh_recip_half_A10.sv +add_fileset_file intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_AGX.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_sigmoid_tanh_recip_half_AGX.sv +add_fileset_file intel_ai_ip/dla_aux_sigmoid_tanh_recip_half_C10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_sigmoid_tanh_recip_half_C10.sv +add_fileset_file intel_ai_ip/dla_aux_pool_control.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_control.sv +add_fileset_file intel_ai_ip/dla_aux_pool_pipeline_stage.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_pipeline_stage.sv +add_fileset_file intel_ai_ip/dla_aux_pool_input_buffer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_input_buffer.sv +add_fileset_file intel_ai_ip/dla_aux_pool_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_pkg.sv +add_fileset_file intel_ai_ip/dla_aux_pool_core.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_core.sv +add_fileset_file intel_ai_ip/dla_aux_pool_config_decoder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_config_decoder.sv +add_fileset_file intel_ai_ip/dla_aux_pool_debug.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_debug.sv +add_fileset_file intel_ai_ip/dla_aux_pool_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_tree.sv +add_fileset_file intel_ai_ip/dla_aux_pool_group.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_group.sv +add_fileset_file intel_ai_ip/dla_aux_pool_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_top.sv +add_fileset_file intel_ai_ip/dla_aux_pool_lane.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_lane.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult_fp16_chain_add.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult_fp16_chain_add.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_pkg.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_core.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_core.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_lane.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_lane.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_config_decoder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_config_decoder.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult_fp16_adder_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult_fp16_adder_tree.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_group.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_group.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_control.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_control.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_fp32_convert.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_fp32_convert.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_filter_bias_cache.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_filter_bias_cache.sv +add_fileset_file intel_ai_ip/dla_s10_adder_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_s10_adder_tree.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_input_buffer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_input_buffer.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_pipeline_stage.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_pipeline_stage.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_top.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult_fp16.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult_fp16.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_shift_register.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_shift_register.sv +add_fileset_file intel_ai_ip/dla_dsp_fp16_mult_sum.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_fp16_mult_sum.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_debug.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_debug.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_lane.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_lane.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_exponent_wrapper.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_exponent_wrapper.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_division_wrapper.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_division_wrapper.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_control.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_control.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_debug.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_debug.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_config_decoder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_config_decoder.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_group.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_group.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_pkg.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_pipeline_stage.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_pipeline_stage.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_top.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_core.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_core.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_input_buffer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_input_buffer.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_division_A10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_division_A10.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_division_AGX.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_division_AGX.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_exponent_S10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_exponent_S10.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_division_C10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_division_C10.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_exponent_C10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_exponent_C10.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_exponent_A10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_exponent_A10.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_division_S10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_division_S10.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_exponent_AGX.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_exponent_AGX.sv +add_fileset_file intel_ai_ip/dla_cdc_reset_sync.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_cdc_reset_sync.sv +add_fileset_file intel_ai_ip/dla_cdc_reset_async.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_cdc_reset_async.sv +add_fileset_file intel_ai_ip/dla_clock_cross_full_sync_internal.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_clock_cross_full_sync_internal.sv +add_fileset_file intel_ai_ip/dla_clock_cross_half_sync_internal.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_clock_cross_half_sync_internal.sv +add_fileset_file intel_ai_ip/dla_clock_cross_half_sync.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_clock_cross_half_sync.sv +add_fileset_file intel_ai_ip/dla_cdc_reset_aligned.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_cdc_reset_aligned.sv +add_fileset_file intel_ai_ip/dla_clock_cross_full_sync.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_clock_cross_full_sync.sv +add_fileset_file intel_ai_ip/dla_aux_dspba_delay_ver.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_dspba_delay_ver.sv +add_fileset_file intel_ai_ip/dla_aux_float_32_to_float_16.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_float_32_to_float_16.sv +add_fileset_file intel_ai_ip/dla_aux_float_16_to_float_32.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_float_16_to_float_32.sv +add_fileset_file intel_ai_ip/dla_config_deserialize.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_config_deserialize.sv +add_fileset_file intel_ai_ip/dla_dsp_fp32_mult_add.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_fp32_mult_add.sv +add_fileset_file intel_ai_ip/dla_fp32_from_fpx_convert.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_fp32_from_fpx_convert.sv +add_fileset_file intel_ai_ip/dla_dsp_prime_tensor_dot_sidefeed.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_prime_tensor_dot_sidefeed.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_pkg.sv +add_fileset_file intel_ai_ip/dla_dsp_prime_tensor_accumulation.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_prime_tensor_accumulation.sv +add_fileset_file intel_ai_ip/dla_value_counter.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_value_counter.sv +add_fileset_file intel_ai_ip/dla_dsp_m18x18_full.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_m18x18_full.sv +add_fileset_file intel_ai_ip/dla_dsp_fp32_mult_acc.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_fp32_mult_acc.sv +add_fileset_file intel_ai_ip/dla_dsp_fp32_add_sub.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_fp32_add_sub.sv +add_fileset_file intel_ai_ip/dla_delay.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_delay.sv +add_fileset_file intel_ai_ip/dla_timer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_timer.sv +add_fileset_file intel_ai_ip/dla_ram.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_ram.sv +add_fileset_file intel_ai_ip/dla_common_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_common_pkg.sv +add_fileset_file intel_ai_ip/dla_counter.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_counter.sv +add_fileset_file intel_ai_ip/dla_latency_alignment.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_latency_alignment.sv +add_fileset_file intel_ai_ip/dla_dsp_m9x9_sumof4.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dsp_m9x9_sumof4.sv +add_fileset_file intel_ai_ip/dla_bitscan_optimized.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_bitscan_optimized.sv +add_fileset_file intel_ai_ip/dla_fp32_to_fpx_convert.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_fp32_to_fpx_convert.sv +add_fileset_file intel_ai_ip/dla_acl_ecc_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_ecc_pkg.sv +add_fileset_file intel_ai_ip/dla_ddrfree_config_data_read.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_ddrfree_config_data_read.sv +add_fileset_file intel_ai_ip/dla_config_network.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_config_network.sv +add_fileset_file intel_ai_ip/dla_config_data_split.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_config_data_split.sv +add_fileset_file intel_ai_ip/dla_config_data_concat.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_config_data_concat.sv +add_fileset_file intel_ai_ip/dla_debug_network_node.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_debug_network_node.sv +add_fileset_file intel_ai_ip/dla_debug_network.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_debug_network.sv +add_fileset_file intel_ai_ip/dla_lt_output_logic.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_output_logic.sv +add_fileset_file intel_ai_ip/dla_lt_mux.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_mux.sv +add_fileset_file intel_ai_ip/dla_lt_data_conversion.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_data_conversion.sv +add_fileset_file intel_ai_ip/dla_lt_step_counter.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_step_counter.sv +add_fileset_file intel_ai_ip/dla_lt_ram_arb.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_ram_arb.sv +add_fileset_file intel_ai_ip/dla_lt_dimension_counter.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_dimension_counter.sv +add_fileset_file intel_ai_ip/dla_lt_gen_index_info.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_gen_index_info.sv +add_fileset_file intel_ai_ip/dla_lt_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_pkg.sv +add_fileset_file intel_ai_ip/dla_lt_funnel.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_funnel.sv +add_fileset_file intel_ai_ip/dla_layout_transform.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_layout_transform.sv +add_fileset_file intel_ai_ip/dla_lt_memory_manager.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_lt_memory_manager.sv +add_fileset_file intel_ai_ip/dla_streamer_fsm.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_streamer_fsm.sv +add_fileset_file intel_ai_ip/dla_input_streamer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_input_streamer.sv +add_fileset_file intel_ai_ip/dla_output_streamer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_output_streamer.sv +add_fileset_file intel_ai_ip/dla_output_streamer_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_output_streamer_pkg.sv +add_fileset_file intel_ai_ip/dla_output_streamer_flush_handler.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_output_streamer_flush_handler.sv +add_fileset_file intel_ai_ip/dla_dma_addr_gen.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_addr_gen.sv +add_fileset_file intel_ai_ip/dla_dma_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_pkg.sv +add_fileset_file intel_ai_ip/dla_dma_writer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_writer.sv +add_fileset_file intel_ai_ip/dla_dma.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma.sv +add_fileset_file intel_ai_ip/dla_dma_csr.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_csr.sv +add_fileset_file intel_ai_ip/dla_dma_reader.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_reader.sv +add_fileset_file intel_ai_ip/dla_dma_read_arb.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_read_arb.sv +add_fileset_file intel_ai_ip/dla_dma_config_intercept.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_config_intercept.sv +add_fileset_file intel_ai_ip/dla_dma_counter_64.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dma_counter_64.sv +add_fileset_file intel_ai_ip/dla_demux_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_demux_pkg.sv +add_fileset_file intel_ai_ip/dla_demux.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_demux.sv +add_fileset_file intel_ai_ip/dla_filter_bias_scale_scratchpad_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_filter_bias_scale_scratchpad_pkg.sv +add_fileset_file intel_ai_ip/dla_filter_bias_scale_scratchpad.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_filter_bias_scale_scratchpad.sv +add_fileset_file intel_ai_ip/dla_acl_mid_speed_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_mid_speed_fifo.sv +add_fileset_file intel_ai_ip/dla_acl_fanout_pipeline.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_fanout_pipeline.sv +add_fileset_file intel_ai_ip/dla_acl_lfsr.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_lfsr.sv +add_fileset_file intel_ai_ip/dla_hld_fifo_zero_width.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_fifo_zero_width.sv +add_fileset_file intel_ai_ip/dla_acl_low_latency_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_low_latency_fifo.sv +add_fileset_file intel_ai_ip/dla_acl_tessellated_incr_decr_threshold.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_tessellated_incr_decr_threshold.sv +add_fileset_file intel_ai_ip/dla_acl_latency_one_ram_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_latency_one_ram_fifo.sv +add_fileset_file intel_ai_ip/dla_acl_std_synchronizer_nocut.v SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_std_synchronizer_nocut.v +add_fileset_file intel_ai_ip/dla_acl_zero_latency_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_zero_latency_fifo.sv +add_fileset_file intel_ai_ip/dla_hld_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_fifo.sv +add_fileset_file intel_ai_ip/dla_acl_latency_zero_ram_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_latency_zero_ram_fifo.sv +add_fileset_file intel_ai_ip/dla_acl_high_speed_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_high_speed_fifo.sv +add_fileset_file intel_ai_ip/dla_acl_tessellated_incr_lookahead.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_tessellated_incr_lookahead.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_word_coalescer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_word_coalescer.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_read_data_alignment.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_read_data_alignment.sv +add_fileset_file intel_ai_ip/dla_hld_global_load_store.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_global_load_store.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_burst_coalescer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_burst_coalescer.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_read_cache.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_read_cache.sv +add_fileset_file intel_ai_ip/dla_hld_lsu.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu.sv +add_fileset_file intel_ai_ip/dla_acl_shift_register_no_reset.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_shift_register_no_reset.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_write_data_alignment.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_write_data_alignment.sv +add_fileset_file intel_ai_ip/dla_acl_burst_splitter.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_acl_burst_splitter.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_unaligned_controller.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_unaligned_controller.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_coalescer_dynamic_timeout.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_coalescer_dynamic_timeout.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_data_aligner.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_data_aligner.sv +add_fileset_file intel_ai_ip/dla_hld_lsu_write_kernel_downstream.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_lsu_write_kernel_downstream.sv +add_fileset_file intel_ai_ip/dla_hld_ram_generic_three_way_depth_stitch.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_generic_three_way_depth_stitch.sv +add_fileset_file intel_ai_ip/dla_hld_ram_tall_depth_stitch.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_tall_depth_stitch.sv +add_fileset_file intel_ai_ip/dla_hld_ram_short_depth_stitch.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_short_depth_stitch.sv +add_fileset_file intel_ai_ip/dla_hld_ram.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram.sv +add_fileset_file intel_ai_ip/dla_hld_ram_generic_two_way_depth_stitch.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_generic_two_way_depth_stitch.sv +add_fileset_file intel_ai_ip/dla_hld_ram_lower_mlab_simple_dual_port.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_lower_mlab_simple_dual_port.sv +add_fileset_file intel_ai_ip/dla_hld_ram_bits_per_enable.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_bits_per_enable.sv +add_fileset_file intel_ai_ip/dla_hld_ram_lower_m20k_simple_dual_port.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_lower_m20k_simple_dual_port.sv +add_fileset_file intel_ai_ip/dla_hld_ram_bottom_depth_stitch.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_bottom_depth_stitch.sv +add_fileset_file intel_ai_ip/dla_hld_ram_remaining_width.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_remaining_width.sv +add_fileset_file intel_ai_ip/dla_hld_ram_bottom_width_stitch.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_bottom_width_stitch.sv +add_fileset_file intel_ai_ip/dla_hld_ram_lower_m20k_true_dual_port.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_lower_m20k_true_dual_port.sv +add_fileset_file intel_ai_ip/dla_hld_ram_ecc.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_ecc.sv +add_fileset_file intel_ai_ip/dla_hld_ram_lower.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_hld_ram_lower.sv +add_fileset_file intel_ai_ip/dla_input_feeder_writer_config.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_input_feeder_writer_config.sv +add_fileset_file intel_ai_ip/dla_input_feeder_reader_config.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_input_feeder_reader_config.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_coord_validate_dim.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_coord_validate_dim.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_manager.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_manager.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_ram.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_ram.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_fp_conversion.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_fp_conversion.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_input_mux.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_input_mux.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_reader_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_reader_top.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_coord_gen.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_coord_gen.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_data_split.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_data_split.sv +add_fileset_file intel_ai_ip/dla_input_feeder_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_input_feeder_pkg.sv +add_fileset_file intel_ai_ip/dla_input_feeder.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_input_feeder.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_fp_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_fp_top.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_coord_validate.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_coord_validate.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_addr_offset_gen.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_addr_offset_gen.sv +add_fileset_file intel_ai_ip/dla_input_feeder_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_input_feeder_if.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_addr_gen_pipeline.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_addr_gen_pipeline.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_max_value.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_max_value.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_top.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_top.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_block_align_mantissa.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_block_align_mantissa.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_reader_addr_gen.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_reader_addr_gen.sv +add_fileset_file intel_ai_ip/dla_stream_buffer_writer_addr_gen.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_stream_buffer_writer_addr_gen.sv +add_fileset_file intel_ai_ip/dla_interface_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_interface_pkg.sv +add_fileset_file intel_ai_ip/dla_interface_profiling_counters.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_interface_profiling_counters.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack2x2_mult6x4.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack2x2_mult6x4.sv +add_fileset_file intel_ai_ip/dla_pe.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_pe.sv +add_fileset_file intel_ai_ip/dla_accum_convert_alm.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_convert_alm.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack2x1_mult7.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack2x1_mult7.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult9_chain_add.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult9_chain_add.sv +add_fileset_file intel_ai_ip/dla_signmag_to_2scomplement.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_signmag_to_2scomplement.sv +add_fileset_file intel_ai_ip/dla_accum_blockfp_dsp.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_blockfp_dsp.sv +add_fileset_file intel_ai_ip/dla_a10_c10_adder_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_a10_c10_adder_tree.sv +add_fileset_file intel_ai_ip/dla_pe_array.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_pe_array.sv +add_fileset_file intel_ai_ip/dla_dot_adder_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_adder_tree.sv +add_fileset_file intel_ai_ip/dla_tensor_block_dot_and_convert.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_tensor_block_dot_and_convert.sv +add_fileset_file intel_ai_ip/dla_accum_fp32_dsp.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_fp32_dsp.sv +add_fileset_file intel_ai_ip/dla_accum.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult9_adder_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult9_adder_tree.sv +add_fileset_file intel_ai_ip/dla_accum_fp32_convert.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_fp32_convert.sv +add_fileset_file intel_ai_ip/dla_accum_convert_dsp.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_convert_dsp.sv +add_fileset_file intel_ai_ip/dla_dot_alm_s10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_alm_s10.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack2x2_mult5.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack2x2_mult5.sv +add_fileset_file intel_ai_ip/dla_dot_sm_alm_s10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_sm_alm_s10.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult9.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult9.sv +add_fileset_file intel_ai_ip/dla_accum_blockfp_alm.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_blockfp_alm.sv +add_fileset_file intel_ai_ip/dla_s10_adder2.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_s10_adder2.sv +add_fileset_file intel_ai_ip/dla_dot_and_convert.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_and_convert.sv +add_fileset_file intel_ai_ip/dla_accum_fixed.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_accum_fixed.sv +add_fileset_file intel_ai_ip/dla_pe_drain.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_pe_drain.sv +add_fileset_file intel_ai_ip/dla_pe_blockfp_to_accum_input.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_pe_blockfp_to_accum_input.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack1x1_mult18.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack1x1_mult18.sv +add_fileset_file intel_ai_ip/dla_s10_adder_tree.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_s10_adder_tree.sv +add_fileset_file intel_ai_ip/dla_dot_alm.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_alm.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack2x2_mult4.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack2x2_mult4.sv +add_fileset_file intel_ai_ip/dla_a10_adder1.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_a10_adder1.sv +add_fileset_file intel_ai_ip/dla_dot_2s_alm_s10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_2s_alm_s10.sv +add_fileset_file intel_ai_ip/dla_c10_adder1.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_c10_adder1.sv +add_fileset_file intel_ai_ip/dla_s10_adder1.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_s10_adder1.sv +add_fileset_file intel_ai_ip/dla_dot.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot.sv +add_fileset_file intel_ai_ip/dla_2scomplement_to_signmag.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_2scomplement_to_signmag.sv +add_fileset_file intel_ai_ip/dla_pe_array_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_pe_array_pkg.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack2x2_mult5x4.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack2x2_mult5x4.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_tensor1x2_mult10_hidden_sideload.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_tensor1x2_mult10_hidden_sideload.sv +add_fileset_file intel_ai_ip/dla_dot_dsp_pack2x2_mult7.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_dsp_pack2x2_mult7.sv +add_fileset_file intel_ai_ip/dla_dot_alm_a10_c10.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_alm_a10_c10.sv +add_fileset_file intel_ai_ip/dla_dot_checker.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_dot_checker.sv +add_fileset_file intel_ai_ip/dla_alm_pipelined_accum.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_alm_pipelined_accum.sv +add_fileset_file intel_ai_ip/dla_exit_fifo_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_exit_fifo_pkg.sv +add_fileset_file intel_ai_ip/dla_sfc_backpressure_generator.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_sfc_backpressure_generator.sv +add_fileset_file intel_ai_ip/dla_exit_fifo.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_exit_fifo.sv +add_fileset_file intel_ai_ip/dla_filter_ddr_unpack.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_filter_ddr_unpack.sv +add_fileset_file intel_ai_ip/dla_sequencer_pe_control.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_sequencer_pe_control.sv +add_fileset_file intel_ai_ip/dla_sequencer_result_id_counters.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_sequencer_result_id_counters.sv +add_fileset_file intel_ai_ip/dla_sequencer_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_sequencer_pkg.sv +add_fileset_file intel_ai_ip/dla_sequencer_scratchpad_control.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_sequencer_scratchpad_control.sv +add_fileset_file intel_ai_ip/dla_sequencer.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_sequencer.sv +add_fileset_file intel_ai_ip/dla_platform_reset.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_platform_reset.sv +add_fileset_file intel_ai_ip/dla_platform_reset_internal.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_platform_reset_internal.sv +add_fileset_file intel_ai_ip/dla_top_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_top_pkg.sv +add_fileset_file intel_ai_ip/dla_width_adapter.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_width_adapter.sv +add_fileset_file intel_ai_ip/dla_width_adapter_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_width_adapter_pkg.sv +add_fileset_file intel_ai_ip/dla_xbar_config_handler.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_xbar_config_handler.sv +add_fileset_file intel_ai_ip/dla_xbar_pkg.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_xbar_pkg.sv +add_fileset_file intel_ai_ip/dla_xbar_wrapper.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_xbar_wrapper.sv +add_fileset_file intel_ai_ip/dla_xbar.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_xbar.sv +add_fileset_file intel_ai_ip/dla_st_pipeline_stage.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_st_pipeline_stage.sv +add_fileset_file intel_ai_ip/dla_aux_activation_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_activation_if.sv +add_fileset_file intel_ai_ip/dla_aux_pool_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_pool_if.sv +add_fileset_file intel_ai_ip/dla_aux_depthwise_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_depthwise_if.sv +add_fileset_file intel_ai_ip/dla_aux_softmax_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_aux_softmax_if.sv +add_fileset_file intel_ai_ip/dla_layout_transform_config.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_layout_transform_config.sv +add_fileset_file intel_ai_ip/dla_filter_bias_scale_scratchpad_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_filter_bias_scale_scratchpad_if.sv +add_fileset_file intel_ai_ip/dla_interface_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_interface_if.sv +add_fileset_file intel_ai_ip/dla_pe_array_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_pe_array_if.sv +add_fileset_file intel_ai_ip/dla_xbar_if.sv SYSTEM_VERILOG PATH ../intel_ai_ip/verilog/dla_xbar_if.sv +add_fileset_file intel_ai_ip/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000116_invTables_lutmem.mif MIF PATH ../intel_ai_ip/verilog/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000116_invTables_lutmem.mif +add_fileset_file intel_ai_ip/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000119_invTables_lutmem.mif MIF PATH ../intel_ai_ip/verilog/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000119_invTables_lutmem.mif +add_fileset_file intel_ai_ip/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0001ock_rsrvd_fix_lutmem.mif MIF PATH ../intel_ai_ip/verilog/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0001ock_rsrvd_fix_lutmem.mif +add_fileset_file intel_ai_ip/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0002ock_rsrvd_fix_lutmem.mif MIF PATH ../intel_ai_ip/verilog/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0002ock_rsrvd_fix_lutmem.mif +add_fileset_file intel_ai_ip/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0000ock_rsrvd_fix_lutmem.mif MIF PATH ../intel_ai_ip/verilog/my_exponent_flt_i_sfc_logic_s_c1_in_wt_e0000ock_rsrvd_fix_lutmem.mif +add_fileset_file intel_ai_ip/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000113_invTables_lutmem.mif MIF PATH ../intel_ai_ip/verilog/my_division_flt_i_sfc_logic_s_c1_in_wt_e0000113_invTables_lutmem.mif +add_fileset_file intel_ai_ip/dla_acl_width_clip.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_acl_width_clip.svh +add_fileset_file intel_ai_ip/dla_aux_activation_functions.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_aux_activation_functions.svh +add_fileset_file intel_ai_ip/dla_aux_activation_constants.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_aux_activation_constants.svh +add_fileset_file intel_ai_ip/dla_vector_dot_arch_info.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_vector_dot_arch_info.svh +add_fileset_file intel_ai_ip/dla_common_types.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_common_types.svh +add_fileset_file intel_ai_ip/dla_constants.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_constants.svh +add_fileset_file intel_ai_ip/dla_common_macros.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_common_macros.svh +add_fileset_file intel_ai_ip/dla_aux_generic_pkg.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_aux_generic_pkg.svh +add_fileset_file intel_ai_ip/dla_aux_generic_debug_pkg.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_aux_generic_debug_pkg.svh +add_fileset_file intel_ai_ip/dla_acl_parameter_assert.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_acl_parameter_assert.svh +add_fileset_file intel_ai_ip/dla_common_enums.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_common_enums.svh +add_fileset_file intel_ai_ip/dla_layout_transform_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_layout_transform_config.svh +add_fileset_file intel_ai_ip/dla_output_streamer_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_output_streamer_config.svh +add_fileset_file intel_ai_ip/dla_dma_config_filter_reader.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_dma_config_filter_reader.svh +add_fileset_file intel_ai_ip/dla_dma_config_feature_reader.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_dma_config_feature_reader.svh +add_fileset_file intel_ai_ip/dla_dma_config_feature_writer.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_dma_config_feature_writer.svh +add_fileset_file intel_ai_ip/dla_dma_config_reader.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_dma_config_reader.svh +add_fileset_file intel_ai_ip/dla_dma_constants.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_dma_constants.svh +add_fileset_file intel_ai_ip/dla_demux_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_demux_config.svh +add_fileset_file intel_ai_ip/dla_filter_bias_scale_scratchpad_arch_info.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_filter_bias_scale_scratchpad_arch_info.svh +add_fileset_file intel_ai_ip/dla_input_feeder_constants.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_constants.svh +add_fileset_file intel_ai_ip/dla_input_feeder_out_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_out_config.svh +add_fileset_file intel_ai_ip/dla_input_feeder_writer_mux_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_writer_mux_config.svh +add_fileset_file intel_ai_ip/dla_input_feeder_sb_xbar_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_sb_xbar_config.svh +add_fileset_file intel_ai_ip/dla_input_feeder_reader_config_vc.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_reader_config_vc.svh +add_fileset_file intel_ai_ip/dla_input_feeder_in_config.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_in_config.svh +add_fileset_file intel_ai_ip/dla_input_feeder_writer_config_vc.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_input_feeder_writer_config_vc.svh +add_fileset_file intel_ai_ip/dla_pe_array_constants.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_pe_array_constants.svh +add_fileset_file intel_ai_ip/dla_pe_array_enums.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_pe_array_enums.svh +add_fileset_file intel_ai_ip/dla_pe_array_arch_t.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_pe_array_arch_t.svh +add_fileset_file intel_ai_ip/dla_top_derived_params.svh SYSTEM_VERILOG_INCLUDE PATH ../intel_ai_ip/verilog/dla_top_derived_params.svh +add_fileset_file intel_ai_ip/dla_clock_cross_sync.sdc SDC PATH ../intel_ai_ip/verilog/dla_clock_cross_sync.sdc |