1 files changed, 41 insertions, 0 deletions
diff --git a/python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_pkg.sv b/python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_pkg.sv
new file mode 100644
index 0000000..ed0d64f
--- /dev/null
+++ b/python/openvino/demo/ip/intel_ai_ip/verilog/dla_output_streamer_pkg.sv
@@ -0,0 +1,41 @@
+// Copyright 2024 Intel Corporation.
+//
+// This software and the related documents are Intel copyrighted materials,
+// and your use of them is governed by the express license under which they
+// were provided to you ("License"). Unless the License provides otherwise,
+// you may not use, modify, copy, publish, distribute, disclose or transmit
+// this software or the related documents without Intel's prior written
+// permission.
+//
+// This software and the related documents are provided as is, with no express
+// or implied warranties, other than those that are expressly stated in the
+// License.
+
+// This package keeps all of the arch parameters related to the output streamer
+// For now it only includes the config struct
+
+`resetall
+`undefineall
+package dla_output_streamer_pkg;
+  import dla_common_pkg::*;
+  `include "dla_output_streamer_config.svh"
+   typedef struct {
+    int TDATA_WIDTH;              // AXI data width
+    int CONFIG_WIDTH;             // typically 32
+    int C_VECTOR;                 // architecture c vector
+    int FIFO_DEPTH;               // depth of the dc data fifo
+    device_family_t DEVICE;       // device
+  } output_streamer_arch_t;
+
+  virtual class data_t #(int DATA_WIDTH);
+    // Define a packed struct for a single data element with the specified width
+    typedef struct packed {
+        logic [DATA_WIDTH-1:0] d;
+    } t;
+  endclass
+
+  virtual class output_streamer_out_data_t #(int WIDTH);
+    typedef data_t#(
+      .DATA_WIDTH(WIDTH))::t t;
+  endclass
+endpackage