diff options
Diffstat (limited to 'python/openvino/demo/models')
| -rw-r--r-- | python/openvino/demo/models/architectures/A10_Small_NoSoftmax.arch | 118 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/AGX7_Small_NoSoftmax.arch | 118 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/agx7_area.arch | 111 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/agx7_area.ptc | 248 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/agx7_performance.arch | 111 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/agx7_performance.ptc | 223 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/de5a_area.arch | 111 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/de5a_performance.arch | 111 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/quartus_ptc.log | 26 | ||||
| -rw-r--r-- | python/openvino/demo/models/architectures/quartus_ptc.rec | 10 | ||||
| -rw-r--r-- | python/openvino/demo/models/model_bmp.bin | bin | 0 -> 1949252 bytes | |||
| -rw-r--r-- | python/openvino/demo/models/model_bmp.xml | 1782 | ||||
| -rw-r--r-- | python/openvino/demo/models/model_bmp_de5a_area.bin | bin | 0 -> 3374709 bytes |
13 files changed, 2969 insertions, 0 deletions
diff --git a/python/openvino/demo/models/architectures/A10_Small_NoSoftmax.arch b/python/openvino/demo/models/architectures/A10_Small_NoSoftmax.arch new file mode 100644 index 0000000..183d50d --- /dev/null +++ b/python/openvino/demo/models/architectures/A10_Small_NoSoftmax.arch @@ -0,0 +1,118 @@ +family : 'A10' +k_vector : 16 +c_vector : 16 +arch_precision : FP11 + +stream_buffer_depth : 17600 + +output_channels_max : 14320 + +enable_debug : false + +pe_array { + num_interleaved_features : 4 + num_interleaved_filters : 1 + exit_fifo_depth : 1024 +} + +filter_scratchpad { + filter_depth : 512 + bias_scale_depth : 512 +} + +dma { + csr_addr_width : 11 + csr_data_bytes : 4 + ddr_addr_width : 32 + ddr_burst_width : 4 + ddr_data_bytes : 64 + ddr_read_id_width : 2 +} + +activation { + generic_aux_parameters { + k_vector : 16 + } + enable_relu : true + enable_leaky_relu : false + enable_sigmoid : false + enable_prelu : false +} + +pool { + generic_aux_parameters { + k_vector : 1 + } + max_window_height : 3 + max_window_width : 3 + max_stride_vertical : 4 + max_stride_horizontal : 4 +} + +xbar { + xbar_k_vector : 16 + max_input_interfaces : 4 + max_output_interfaces : 4 + xbar_ports { + xbar_aux_port { + name : 'activation' + input_connection : 'xbar_in_port' + } + xbar_aux_port { + name : 'pool' + input_connection : 'xbar_in_port' + input_connection : 'activation' + } + } + xbar_in_port { + external_connection : 'pe_array' + } + xbar_out_port { + external_connection : 'input_feeder' + external_connection : 'output_writer' + input_connection : 'xbar_in_port' + input_connection : 'pool' + input_connection : 'activation' + } +} + +config_network { + modules { + module { + name : 'filter_reader' + cross_clock : 1 + } + module { + name : 'input_feeder_mux' + } + module { + name : 'input_feeder_writer' + } + module { + name : 'input_feeder_in' + } + module { + name : 'input_feeder_reader' + } + module { + name : 'input_feeder_out' + } + module { + name : 'feature_writer' + cross_clock : 1 + } + module { + name : 'feature_reader' + cross_clock : 1 + } + module { + name : 'xbar' + } + module { + name : 'activation' + } + module { + name : 'pool' + } + } +} diff --git a/python/openvino/demo/models/architectures/AGX7_Small_NoSoftmax.arch b/python/openvino/demo/models/architectures/AGX7_Small_NoSoftmax.arch new file mode 100644 index 0000000..531bc91 --- /dev/null +++ b/python/openvino/demo/models/architectures/AGX7_Small_NoSoftmax.arch @@ -0,0 +1,118 @@ +family : 'AGX7' +k_vector : 16 +c_vector : 16 +arch_precision : FP11 + +stream_buffer_depth : 17600 + +output_channels_max : 14320 + +enable_debug : false + +pe_array { + num_interleaved_features : 5 + num_interleaved_filters : 1 + exit_fifo_depth : 1024 +} + +filter_scratchpad { + filter_depth : 512 + bias_scale_depth : 512 +} + +dma { + csr_addr_width : 11 + csr_data_bytes : 4 + ddr_addr_width : 32 + ddr_burst_width : 4 + ddr_data_bytes : 64 + ddr_read_id_width : 2 +} + +activation { + generic_aux_parameters { + k_vector : 16 + } + enable_relu : true + enable_leaky_relu : false + enable_sigmoid : false + enable_prelu : false +} + +pool { + generic_aux_parameters { + k_vector : 1 + } + max_window_height : 3 + max_window_width : 3 + max_stride_vertical : 4 + max_stride_horizontal : 4 +} + +xbar { + xbar_k_vector : 16 + max_input_interfaces : 4 + max_output_interfaces : 4 + xbar_ports { + xbar_aux_port { + name : 'activation' + input_connection : 'xbar_in_port' + } + xbar_aux_port { + name : 'pool' + input_connection : 'xbar_in_port' + input_connection : 'activation' + } + } + xbar_in_port { + external_connection : 'pe_array' + } + xbar_out_port { + external_connection : 'input_feeder' + external_connection : 'output_writer' + input_connection : 'xbar_in_port' + input_connection : 'pool' + input_connection : 'activation' + } +} + +config_network { + modules { + module { + name : 'filter_reader' + cross_clock : 1 + } + module { + name : 'input_feeder_mux' + } + module { + name : 'input_feeder_writer' + } + module { + name : 'input_feeder_in' + } + module { + name : 'input_feeder_reader' + } + module { + name : 'input_feeder_out' + } + module { + name : 'feature_writer' + cross_clock : 1 + } + module { + name : 'feature_reader' + cross_clock : 1 + } + module { + name : 'xbar' + } + module { + name : 'activation' + } + module { + name : 'pool' + } + } +} diff --git a/python/openvino/demo/models/architectures/agx7_area.arch b/python/openvino/demo/models/architectures/agx7_area.arch new file mode 100644 index 0000000..4b64070 --- /dev/null +++ b/python/openvino/demo/models/architectures/agx7_area.arch @@ -0,0 +1,111 @@ +k_vector: 32 +c_vector: 32 +family: "AGX7" +arch_precision: FP11 +filter_precision: FP11 +sb_precision: FP11 +output_channels_max: 14320 +enable_debug: false +stream_buffer_depth: 6148 +dma { + csr_addr_width: 11 + csr_data_bytes: 4 + ddr_addr_width: 32 + ddr_burst_width: 4 + ddr_data_bytes: 64 + ddr_read_id_width: 2 +} +config_network { + modules { + module { + name: "filter_reader" + cross_clock: 1 + } + module { + name: "input_feeder_mux" + } + module { + name: "input_feeder_writer" + } + module { + name: "input_feeder_in" + } + module { + name: "input_feeder_reader" + } + module { + name: "input_feeder_out" + } + module { + name: "feature_writer" + cross_clock: 1 + } + module { + name: "feature_reader" + cross_clock: 1 + } + module { + name: "xbar" + } + module { + name: "activation" + } + module { + name: "pool" + } + } +} +xbar { + xbar_k_vector: 4 + max_input_interfaces: 4 + max_output_interfaces: 4 + xbar_ports { + xbar_aux_port { + name: "activation" + input_connection: "xbar_in_port" + } + xbar_aux_port { + name: "pool" + input_connection: "xbar_in_port" + input_connection: "activation" + } + } + xbar_in_port { + external_connection: "pe_array" + } + xbar_out_port { + external_connection: "input_feeder" + external_connection: "output_writer" + input_connection: "xbar_in_port" + input_connection: "pool" + input_connection: "activation" + } +} +activation { + generic_aux_parameters { + k_vector: 4 + } + enable_relu: true + enable_leaky_relu: false + enable_prelu: false + enable_sigmoid: false +} +pool { + generic_aux_parameters { + k_vector: 4 + } + max_window_height: 3 + max_window_width: 3 + max_stride_vertical: 4 + max_stride_horizontal: 4 +} +pe_array { + dsp_limit: 8528 + num_interleaved_features: 5 + num_interleaved_filters: 1 + exit_fifo_depth: 1024 +} +filter_scratchpad { + filter_depth: 512 + bias_scale_depth: 512 +} diff --git a/python/openvino/demo/models/architectures/agx7_area.ptc b/python/openvino/demo/models/architectures/agx7_area.ptc new file mode 100644 index 0000000..feb1a77 --- /dev/null +++ b/python/openvino/demo/models/architectures/agx7_area.ptc @@ -0,0 +1,248 @@ +{ + "blocks": { + "apply_margin_group": [ + { + "ThermalApplyMargin": "0%" + } + ], + "auto_compute_tj_group": [ + { + "Main_AUTO_COMPUTE_TJ": "Detailed Thermal Model" + } + ], + "calc_mode_group": [ + { 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supported" + } + ], + "xcvr_grade_definition": [ + { + "XCVRGrade": "F2" + } + ], + "xcvr_unused_banks_group": [ + { + "HSSIUSERINPUT_UNUSED_HSSI_BANKS": "Power Down Unused Transceivers" + } + ] + }, + "header": { + "EPE_IMPORT_VERSION": "4.11" + }, + "ips": {} +} diff --git a/python/openvino/demo/models/architectures/agx7_performance.arch b/python/openvino/demo/models/architectures/agx7_performance.arch new file mode 100644 index 0000000..15e535a --- /dev/null +++ b/python/openvino/demo/models/architectures/agx7_performance.arch @@ -0,0 +1,111 @@ +k_vector: 128 +c_vector: 64 +family: "AGX7" +arch_precision: FP11 +filter_precision: FP11 +sb_precision: FP11 +output_channels_max: 14320 +enable_debug: false +stream_buffer_depth: 98441 +dma { + csr_addr_width: 11 + csr_data_bytes: 4 + ddr_addr_width: 32 + ddr_burst_width: 4 + ddr_data_bytes: 64 + ddr_read_id_width: 2 +} +config_network { + modules { + module { + name: "filter_reader" + cross_clock: 1 + } + module { + name: "input_feeder_mux" + } + module { + name: "input_feeder_writer" + } + module { + name: "input_feeder_in" + } + module { + name: "input_feeder_reader" + } + module { + name: "input_feeder_out" + } + module { + name: "feature_writer" + cross_clock: 1 + } + module { + name: "feature_reader" + cross_clock: 1 + } + module { + name: "xbar" + } + module { + name: "activation" + } + module { + name: "pool" + } + } +} +xbar { + xbar_k_vector: 64 + max_input_interfaces: 4 + max_output_interfaces: 4 + xbar_ports { + xbar_aux_port { + name: "activation" + input_connection: "xbar_in_port" + } + xbar_aux_port { + name: "pool" + input_connection: "xbar_in_port" + input_connection: "activation" + } + } + xbar_in_port { + external_connection: "pe_array" + } + xbar_out_port { + external_connection: "input_feeder" + external_connection: "output_writer" + input_connection: "xbar_in_port" + input_connection: "pool" + input_connection: "activation" + } +} +activation { + generic_aux_parameters { + k_vector: 64 + } + enable_relu: true + enable_leaky_relu: false + enable_prelu: false + enable_sigmoid: false +} +pool { + generic_aux_parameters { + k_vector: 64 + } + max_window_height: 3 + max_window_width: 3 + max_stride_vertical: 4 + max_stride_horizontal: 4 +} +pe_array { + dsp_limit: 8528 + num_interleaved_features: 5 + num_interleaved_filters: 1 + exit_fifo_depth: 1024 +} +filter_scratchpad { + filter_depth: 512 + bias_scale_depth: 512 +} diff --git a/python/openvino/demo/models/architectures/agx7_performance.ptc b/python/openvino/demo/models/architectures/agx7_performance.ptc new file mode 100644 index 0000000..00aad89 --- /dev/null +++ b/python/openvino/demo/models/architectures/agx7_performance.ptc @@ -0,0 +1,223 @@ +{ + "blocks": { + "apply_margin_group": [ + { + "ThermalApplyMargin": "0%" + } + ], + "auto_compute_tj_group": [ + { + "Main_AUTO_COMPUTE_TJ": "Detailed Thermal Model" + } + ], + "calc_mode_group": [ + { + "ThermalCalcMode": "Find cooling solution for maximum junction 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"DSPUSERINPUT_CONFIG": "Sum of 4 9X9", + "DSPUSERINPUT_INSTANCE_PATH": "", + "DSPUSERINPUT_MODULE": "", + "DSPUSERINPUT_NUM_INSTANCES": "2176", + "DSPUSERINPUT_PREADDER": "No", + "DSPUSERINPUT_REGISTERED_STAGES": "4", + "DSPUSERINPUT_TOGGLE_RATE": "12.5%", + "DSPUSERINPUT_USER_COMMENTS": "" + } + ], + "family_definition": [ + { + "Family": "Agilex 7" + } + ], + "hbm_freq_group": [ + { + "HBMUSERINPUT_HBM0_FREQUENCY": "0", + "HBMUSERINPUT_HBM1_FREQUENCY": "0" + } + ], + "io_unused_banks_group": [ + { + "IOUSERINPUT_UNUSED_HVIO_BANKS": "N/A", + "IOUSERINPUT_UNUSED_IO_BANKS": "1.2V" + } + ], + "logic_row_group": [ + { + "LOGICUSERINPUT_CLOCK_FREQ": "1000", + "LOGICUSERINPUT_INSTANCE_PATH": "", + "LOGICUSERINPUT_MODULE": "", + "LOGICUSERINPUT_NUM_FF": "551076", + "LOGICUSERINPUT_NUM_HALF_ALM": "217620", + "LOGICUSERINPUT_ROUTING_FACTOR": "3", + "LOGICUSERINPUT_TOGGLE_RATE": "12.5%", + "LOGICUSERINPUT_USER_COMMENTS": "" + } + ], + "package_definition": [ + { + "Package": "R24C" + } + ], + "power_char_definition": [ + { + "PowerChar": "Maximum" + } + ], + "ram_row_group": [ + { + "RAMUSERINPUT_BLOCK_ID": "N/A", + "RAMUSERINPUT_DEPTH": "512", + "RAMUSERINPUT_INSTANCE_PATH": "", + "RAMUSERINPUT_MODE": "Simple Dual Port", + "RAMUSERINPUT_MODULE": "", + "RAMUSERINPUT_NUM_BLOCKS": "1754", + "RAMUSERINPUT_PORT_A_CLOCK_FREQ": "1000", + "RAMUSERINPUT_PORT_A_ENABLE": "100%", + "RAMUSERINPUT_PORT_A_RDEN": "0%", + "RAMUSERINPUT_PORT_A_WREN": "50%", + "RAMUSERINPUT_PORT_B_CLOCK_FREQ": "1000", + "RAMUSERINPUT_PORT_B_ENABLE": "100%", + "RAMUSERINPUT_PORT_B_RDEN": "100%", + "RAMUSERINPUT_PORT_B_WREN": "0%", + "RAMUSERINPUT_PORT_C_WREN": "0%", + "RAMUSERINPUT_PORT_D_RDEN": "0%", + "RAMUSERINPUT_TOGGLE_RATE": "12.5%", + "RAMUSERINPUT_TYPE": "M20K", + "RAMUSERINPUT_UNOC_MODE": "N/A", + "RAMUSERINPUT_UNOC_PORT_ENABLE": "N/A", + "RAMUSERINPUT_UNOC_PORT_WREN": "N/A", + "RAMUSERINPUT_USER_COMMENTS": "", + "RAMUSERINPUT_WIDTH": "40" + }, + { + "RAMUSERINPUT_BLOCK_ID": "N/A", + "RAMUSERINPUT_DEPTH": "2048", + "RAMUSERINPUT_INSTANCE_PATH": "", + "RAMUSERINPUT_MODE": "Simple Dual Port", + "RAMUSERINPUT_MODULE": "", + "RAMUSERINPUT_NUM_BLOCKS": "2208", + "RAMUSERINPUT_PORT_A_CLOCK_FREQ": "1000", + "RAMUSERINPUT_PORT_A_ENABLE": "100%", + "RAMUSERINPUT_PORT_A_RDEN": "0%", + "RAMUSERINPUT_PORT_A_WREN": "50%", + "RAMUSERINPUT_PORT_B_CLOCK_FREQ": "1000", + "RAMUSERINPUT_PORT_B_ENABLE": "100%", + "RAMUSERINPUT_PORT_B_RDEN": "100%", + "RAMUSERINPUT_PORT_B_WREN": "0%", + "RAMUSERINPUT_PORT_C_WREN": "0%", + "RAMUSERINPUT_PORT_D_RDEN": "0%", + "RAMUSERINPUT_TOGGLE_RATE": "12.5%", + "RAMUSERINPUT_TYPE": "M20K", + "RAMUSERINPUT_UNOC_MODE": "N/A", + "RAMUSERINPUT_UNOC_PORT_ENABLE": "N/A", + "RAMUSERINPUT_UNOC_PORT_WREN": "N/A", + "RAMUSERINPUT_USER_COMMENTS": "", + "RAMUSERINPUT_WIDTH": "10" + }, + { + "RAMUSERINPUT_BLOCK_ID": "N/A", + "RAMUSERINPUT_DEPTH": "2048", + "RAMUSERINPUT_INSTANCE_PATH": "", + "RAMUSERINPUT_MODE": "Simple Dual Port", + "RAMUSERINPUT_MODULE": "", + "RAMUSERINPUT_NUM_BLOCKS": "129", + "RAMUSERINPUT_PORT_A_CLOCK_FREQ": "1000", + "RAMUSERINPUT_PORT_A_ENABLE": "100%", + "RAMUSERINPUT_PORT_A_RDEN": "0%", + "RAMUSERINPUT_PORT_A_WREN": "50%", + "RAMUSERINPUT_PORT_B_CLOCK_FREQ": "1000", + "RAMUSERINPUT_PORT_B_ENABLE": "100%", + "RAMUSERINPUT_PORT_B_RDEN": "100%", + "RAMUSERINPUT_PORT_B_WREN": "0%", + "RAMUSERINPUT_PORT_C_WREN": "0%", + "RAMUSERINPUT_PORT_D_RDEN": "0%", + "RAMUSERINPUT_TOGGLE_RATE": "12.5%", + "RAMUSERINPUT_TYPE": "M20K", + "RAMUSERINPUT_UNOC_MODE": "N/A", + "RAMUSERINPUT_UNOC_PORT_ENABLE": "N/A", + "RAMUSERINPUT_UNOC_PORT_WREN": "N/A", + "RAMUSERINPUT_USER_COMMENTS": "", + "RAMUSERINPUT_WIDTH": "10" + } + ], + "temp_grade_definition": [ + { + "TempGrade": "Extended -4 Extreme Low Power" + } + ], + "thermal_inputs_group": [ + { + "ThermalPsiCAInput": "N/A", + "ThermalTA": "25", + "ThermalTJMAX": "100" + } + ], + "thermal_parameters": [ + { + "Main_User_Tj": "N/A" + } + ], + "thermal_recalc_group": [ + { + "ThermalRecalcMode": "Automatic" + } + ], + "tsd_method_group": [ + { + "ThermalTsdMethod": "Not supported" + } + ], + "xcvr_grade_definition": [ + { + "XCVRGrade": "F2" + } + ], + "xcvr_unused_banks_group": [ + { + "HSSIUSERINPUT_UNUSED_HSSI_BANKS": "Power Down Unused Transceivers" + } + ] + }, + "header": { + "EPE_IMPORT_VERSION": "4.11" + }, + "ips": {} +} diff --git a/python/openvino/demo/models/architectures/de5a_area.arch b/python/openvino/demo/models/architectures/de5a_area.arch new file mode 100644 index 0000000..b881516 --- /dev/null +++ b/python/openvino/demo/models/architectures/de5a_area.arch @@ -0,0 +1,111 @@ +k_vector: 16 +c_vector: 4 +family: "A10" +arch_precision: FP11 +filter_precision: FP11 +sb_precision: FP11 +output_channels_max: 14320 +enable_debug: false +stream_buffer_depth: 5120 +dma { + csr_addr_width: 11 + csr_data_bytes: 4 + ddr_addr_width: 32 + ddr_burst_width: 4 + ddr_data_bytes: 64 + ddr_read_id_width: 2 +} +config_network { + modules { + module { + name: "filter_reader" + cross_clock: 1 + } + module { + name: "input_feeder_mux" + } + module { + name: "input_feeder_writer" + } + module { + name: "input_feeder_in" + } + module { + name: "input_feeder_reader" + } + module { + name: "input_feeder_out" + } + module { + name: "feature_writer" + cross_clock: 1 + } + module { + name: "feature_reader" + cross_clock: 1 + } + module { + name: "xbar" + } + module { + name: "activation" + } + module { + name: "pool" + } + } +} +xbar { + xbar_k_vector: 4 + max_input_interfaces: 4 + max_output_interfaces: 4 + xbar_ports { + xbar_aux_port { + name: "activation" + input_connection: "xbar_in_port" + } + xbar_aux_port { + name: "pool" + input_connection: "xbar_in_port" + input_connection: "activation" + } + } + xbar_in_port { + external_connection: "pe_array" + } + xbar_out_port { + external_connection: "input_feeder" + external_connection: "output_writer" + input_connection: "xbar_in_port" + input_connection: "pool" + input_connection: "activation" + } +} +activation { + generic_aux_parameters { + k_vector: 4 + } + enable_relu: true + enable_leaky_relu: false + enable_prelu: false + enable_sigmoid: false +} +pool { + generic_aux_parameters { + k_vector: 1 + } + max_window_height: 3 + max_window_width: 3 + max_stride_vertical: 4 + max_stride_horizontal: 4 +} +pe_array { + dsp_limit: 1518 + num_interleaved_features: 4 + num_interleaved_filters: 1 + exit_fifo_depth: 1024 +} +filter_scratchpad { + filter_depth: 512 + bias_scale_depth: 512 +} diff --git a/python/openvino/demo/models/architectures/de5a_performance.arch b/python/openvino/demo/models/architectures/de5a_performance.arch new file mode 100644 index 0000000..548e6be --- /dev/null +++ b/python/openvino/demo/models/architectures/de5a_performance.arch @@ -0,0 +1,111 @@ +k_vector: 64 +c_vector: 64 +family: "A10" +arch_precision: FP11 +filter_precision: FP11 +sb_precision: FP11 +output_channels_max: 14320 +enable_debug: false +stream_buffer_depth: 2088 +dma { + csr_addr_width: 11 + csr_data_bytes: 4 + ddr_addr_width: 32 + ddr_burst_width: 4 + ddr_data_bytes: 64 + ddr_read_id_width: 2 +} +config_network { + modules { + module { + name: "filter_reader" + cross_clock: 1 + } + module { + name: "input_feeder_mux" + } + module { + name: "input_feeder_writer" + } + module { + name: "input_feeder_in" + } + module { + name: "input_feeder_reader" + } + module { + name: "input_feeder_out" + } + module { + name: "feature_writer" + cross_clock: 1 + } + module { + name: "feature_reader" + cross_clock: 1 + } + module { + name: "xbar" + } + module { + name: "activation" + } + module { + name: "pool" + } + } +} +xbar { + xbar_k_vector: 64 + max_input_interfaces: 4 + max_output_interfaces: 4 + xbar_ports { + xbar_aux_port { + name: "activation" + input_connection: "xbar_in_port" + } + xbar_aux_port { + name: "pool" + input_connection: "xbar_in_port" + input_connection: "activation" + } + } + xbar_in_port { + external_connection: "pe_array" + } + xbar_out_port { + external_connection: "input_feeder" + external_connection: "output_writer" + input_connection: "xbar_in_port" + input_connection: "pool" + input_connection: "activation" + } +} +activation { + generic_aux_parameters { + k_vector: 64 + } + enable_relu: true + enable_leaky_relu: false + enable_prelu: false + enable_sigmoid: false +} +pool { + generic_aux_parameters { + k_vector: 64 + } + max_window_height: 3 + max_window_width: 3 + max_stride_vertical: 4 + max_stride_horizontal: 4 +} +pe_array { + dsp_limit: 1518 + num_interleaved_features: 4 + num_interleaved_filters: 1 + exit_fifo_depth: 1024 +} +filter_scratchpad { + filter_depth: 512 + bias_scale_depth: 512 +} diff --git a/python/openvino/demo/models/architectures/quartus_ptc.log b/python/openvino/demo/models/architectures/quartus_ptc.log new file mode 100644 index 0000000..ee09f4b --- /dev/null +++ b/python/openvino/demo/models/architectures/quartus_ptc.log @@ -0,0 +1,26 @@ +# ************************************************** +# Quartus Prime Version 24.3.0 +# Process ID 466429 +# Start logging UI actions +# Fri Jan 24 10:32:12 2025 +# ************************************************** +[Fri Jan 24 10:32:16 2025] Window title: 'Device selection' | 'majorFilter_0' combo box changed to: 'Agilex 7' +[Fri Jan 24 10:32:38 2025] Window title: 'Device selection' | QPushButton '&Close' pressed! +[Fri Jan 24 10:32:40 2025] Window title: 'PTC Error' | QPushButton '&OK' pressed! +[Fri Jan 24 10:32:55 2025] Window title: 'PTC Error' | QPushButton '&OK' pressed! +[Fri Jan 24 10:32:56 2025] Window title: 'Quartus Prime Power and Thermal Calculator Pro Edition - [agx7_area.ptc][*]' | 'Device' combo box changed to: 'AGFB014R24A' +[Fri Jan 24 10:35:19 2025] Window title: 'Device selection' | 'majorFilter_0' combo box changed to: 'Agilex 7' +[Fri Jan 24 10:36:24 2025] Window title: 'Device selection' | QPushButton 'Select Device' pressed! +[Fri Jan 24 10:37:10 2025] Window title: 'PTC Error' | QPushButton '&OK' pressed! +[Fri Jan 24 10:37:13 2025] Window title: 'Quartus Prime Power and Thermal Calculator Pro Edition - [agx7_area.ptc][*]' | 'ThermalRecalcMode' combo box changed to: 'Automatic' +[Fri Jan 24 10:37:15 2025] Window title: 'Quartus Prime Power and Thermal Calculator Pro Edition - [agx7_area.ptc][*]' | 'ThermalRecalcMode' combo box changed to: 'Manual' +[Fri Jan 24 10:40:30 2025] Window title: 'PTC Error' | QPushButton '&OK' pressed! +[Fri Jan 24 10:40:36 2025] [Action triggered] Window title: 'Quartus Prime Power and Thermal Calculator Pro Edition - [agx7_area.ptc][*]' | &File > '&Open...' was pressed +[Fri Jan 24 10:40:38 2025] Window title: 'Open PTC File' | QPushButton '&Open' pressed! +[Fri Jan 24 10:40:40 2025] Window title: 'Quartus Prime' | QPushButton '&No' pressed! +[Fri Jan 24 10:40:45 2025] Window title: 'PTC Error' | QPushButton '&OK' pressed! +[Fri Jan 24 10:40:52 2025] Window title: 'Quartus Prime' | QPushButton '&No' pressed! +# ************************************************** +# Fri Jan 24 10:40:52 2025 +# End of logging UI actions +# ************************************************** diff --git a/python/openvino/demo/models/architectures/quartus_ptc.rec b/python/openvino/demo/models/architectures/quartus_ptc.rec new file mode 100644 index 0000000..9221267 --- /dev/null +++ b/python/openvino/demo/models/architectures/quartus_ptc.rec @@ -0,0 +1,10 @@ +# ************************************************** +# Quartus Prime Version 24.3.0 +# Process ID 466429 +# Start logging TCL commands +# Fri Jan 24 10:32:12 2025 +# ************************************************** +# ************************************************** +# Fri Jan 24 10:40:52 2025 +# End of logging TCL commands +# ************************************************** diff --git a/python/openvino/demo/models/model_bmp.bin b/python/openvino/demo/models/model_bmp.bin Binary files differnew file mode 100644 index 0000000..12bf262 --- /dev/null +++ b/python/openvino/demo/models/model_bmp.bin diff --git a/python/openvino/demo/models/model_bmp.xml b/python/openvino/demo/models/model_bmp.xml new file mode 100644 index 0000000..7cd188d --- /dev/null +++ b/python/openvino/demo/models/model_bmp.xml @@ -0,0 +1,1782 @@ +<?xml version="1.0"?> +<net name="main_graph" version="11"> + <layers> + <layer id="0" name="input.1" type="Parameter" version="opset1"> + <data shape="32,3,128,128" element_type="f32" /> + <output> + <port id="0" precision="FP32" names="input.1"> + <dim>32</dim> + <dim>3</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="1" name="onnx::Conv_174" type="Const" version="opset1"> + <data element_type="f32" shape="16, 3, 3, 3" offset="0" size="1728" /> + <output> + <port id="0" precision="FP32" names="onnx::Conv_174"> + <dim>16</dim> + <dim>3</dim> + <dim>3</dim> + <dim>3</dim> + </port> + </output> + </layer> + <layer id="2" name="/conv2x_0/conv2x_0.0/Conv/WithoutBiases" type="Convolution" version="opset1"> + <data strides="1, 1" dilations="1, 1" pads_begin="1, 1" pads_end="1, 1" auto_pad="explicit" /> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>3</dim> + <dim>128</dim> + <dim>128</dim> + </port> + <port id="1" precision="FP32"> + <dim>16</dim> + <dim>3</dim> + <dim>3</dim> + <dim>3</dim> + </port> + </input> + <output> + <port id="2" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="3" name="Reshape_44" type="Const" version="opset1"> + <data element_type="f32" shape="1, 16, 1, 1" offset="1728" size="64" /> + <output> + <port id="0" precision="FP32"> + <dim>1</dim> + <dim>16</dim> + <dim>1</dim> + <dim>1</dim> + </port> + </output> + </layer> + <layer id="4" name="/conv2x_0/conv2x_0.0/Conv" type="Add" version="opset1"> + <data auto_broadcast="numpy" /> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + <port id="1" precision="FP32"> + <dim>1</dim> + <dim>16</dim> + <dim>1</dim> + <dim>1</dim> + </port> + </input> + <output> + <port id="2" precision="FP32" names="/conv2x_0/conv2x_0.0/Conv_output_0"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="5" name="/conv2x_0/conv2x_0.2/Relu" type="ReLU" version="opset1"> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </input> + <output> + <port id="1" precision="FP32" names="/conv2x_0/conv2x_0.2/Relu_output_0"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="6" name="onnx::Conv_177" type="Const" version="opset1"> + <data element_type="f32" shape="16, 16, 3, 3" offset="1792" size="9216" /> + <output> + <port id="0" precision="FP32" names="onnx::Conv_177"> + <dim>16</dim> + <dim>16</dim> + <dim>3</dim> + <dim>3</dim> + </port> + </output> + </layer> + <layer id="7" name="/conv2x_0/conv2x_0.3/Conv/WithoutBiases" type="Convolution" version="opset1"> + <data strides="1, 1" dilations="1, 1" pads_begin="1, 1" pads_end="1, 1" auto_pad="explicit" /> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + <port id="1" precision="FP32"> + <dim>16</dim> + <dim>16</dim> + <dim>3</dim> + <dim>3</dim> + </port> + </input> + <output> + <port id="2" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="8" name="Reshape_61" type="Const" version="opset1"> + <data element_type="f32" shape="1, 16, 1, 1" offset="11008" size="64" /> + <output> + <port id="0" precision="FP32"> + <dim>1</dim> + <dim>16</dim> + <dim>1</dim> + <dim>1</dim> + </port> + </output> + </layer> + <layer id="9" name="/conv2x_0/conv2x_0.3/Conv" type="Add" version="opset1"> + <data auto_broadcast="numpy" /> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + <port id="1" precision="FP32"> + <dim>1</dim> + <dim>16</dim> + <dim>1</dim> + <dim>1</dim> + </port> + </input> + <output> + <port id="2" precision="FP32" names="/conv2x_0/conv2x_0.3/Conv_output_0"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="10" name="/conv2x_0/conv2x_0.5/Relu" type="ReLU" version="opset1"> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </input> + <output> + <port id="1" precision="FP32" names="/conv2x_0/conv2x_0.5/Relu_output_0"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </output> + </layer> + <layer id="11" name="/pool/MaxPool" type="MaxPool" version="opset8"> + <data strides="2, 2" dilations="1, 1" pads_begin="0, 0" pads_end="0, 0" kernel="2, 2" rounding_type="floor" auto_pad="explicit" index_element_type="i64" axis="0" /> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + <dim>16</dim> + <dim>128</dim> + <dim>128</dim> + </port> + </input> + <output> + <port id="1" precision="FP32" names="/pool/MaxPool_output_0"> + <dim>32</dim> + <dim>16</dim> + <dim>64</dim> + <dim>64</dim> + </port> + <port id="2" precision="I64"> + <dim>32</dim> + <dim>16</dim> + <dim>64</dim> + <dim>64</dim> + </port> + </output> + </layer> + <layer id="12" name="onnx::Conv_180" type="Const" version="opset1"> + <data element_type="f32" shape="32, 16, 3, 3" offset="11072" size="18432" /> + <output> + <port id="0" precision="FP32" names="onnx::Conv_180"> + <dim>32</dim> + <dim>16</dim> + <dim>3</dim> + <dim>3</dim> + </port> + </output> + </layer> + <layer id="13" name="/conv2x_1/conv2x_1.0/Conv/WithoutBiases" type="Convolution" version="opset1"> + <data strides="1, 1" dilations="1, 1" pads_begin="1, 1" pads_end="1, 1" auto_pad="explicit" /> + <input> + <port id="0" precision="FP32"> + <dim>32</dim> + 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