diff options
Diffstat (limited to 'python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.v')
| -rw-r--r-- | python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.v | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.v b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.v new file mode 100644 index 0000000..22d8616 --- /dev/null +++ b/python/openvino/demo/quartus/ip/pet_reconstruction_ip/pet_reconstruction_ip_inst.v @@ -0,0 +1,55 @@ + pet_reconstruction_ip u0 ( + .dla_clk (_connected_to_dla_clk_), // input, width = 1, dla_clk.clk + .ddr_clk (_connected_to_ddr_clk_), // input, width = 1, ddr_clk.clk + .irq_clk (_connected_to_irq_clk_), // input, width = 1, irq_clk.clk + .dla_resetn (_connected_to_dla_resetn_), // input, width = 1, dla_resetn.reset_n + .csr_axi_awaddr (_connected_to_csr_axi_awaddr_), // input, width = 11, csr_axi.awaddr + .csr_axi_awvalid (_connected_to_csr_axi_awvalid_), // input, width = 1, .awvalid + .csr_axi_awready (_connected_to_csr_axi_awready_), // output, width = 1, .awready + .csr_axi_wdata (_connected_to_csr_axi_wdata_), // input, width = 32, .wdata + .csr_axi_wready (_connected_to_csr_axi_wready_), // output, width = 1, .wready + .csr_axi_wvalid (_connected_to_csr_axi_wvalid_), // input, width = 1, .wvalid + .csr_axi_wstrb (_connected_to_csr_axi_wstrb_), // input, width = 4, .wstrb + .csr_axi_bresp (_connected_to_csr_axi_bresp_), // output, width = 2, .bresp + .csr_axi_bvalid (_connected_to_csr_axi_bvalid_), // output, width = 1, .bvalid + .csr_axi_bready (_connected_to_csr_axi_bready_), // input, width = 1, .bready + .csr_axi_rdata (_connected_to_csr_axi_rdata_), // output, width = 32, .rdata + .csr_axi_rresp (_connected_to_csr_axi_rresp_), // output, width = 2, .rresp + .csr_axi_rvalid (_connected_to_csr_axi_rvalid_), // output, width = 1, .rvalid + .csr_axi_rready (_connected_to_csr_axi_rready_), // input, width = 1, .rready + .csr_axi_araddr (_connected_to_csr_axi_araddr_), // input, width = 11, .araddr + .csr_axi_arvalid (_connected_to_csr_axi_arvalid_), // input, width = 1, .arvalid + .csr_axi_arready (_connected_to_csr_axi_arready_), // output, width = 1, .arready + .csr_axi_awprot (_connected_to_csr_axi_awprot_), // input, width = 3, .awprot + .csr_axi_arprot (_connected_to_csr_axi_arprot_), // input, width = 3, .arprot + .ddr_axi_awvalid (_connected_to_ddr_axi_awvalid_), // output, width = 1, ddr_axi.awvalid + .ddr_axi_awprot (_connected_to_ddr_axi_awprot_), // output, width = 3, .awprot + .ddr_axi_awlen (_connected_to_ddr_axi_awlen_), // output, width = 8, .awlen + .ddr_axi_awready (_connected_to_ddr_axi_awready_), // input, width = 1, .awready + .ddr_axi_awsize (_connected_to_ddr_axi_awsize_), // output, width = 3, .awsize + .ddr_axi_awburst (_connected_to_ddr_axi_awburst_), // output, width = 2, .awburst + .ddr_axi_arvalid (_connected_to_ddr_axi_arvalid_), // output, width = 1, .arvalid + .ddr_axi_arprot (_connected_to_ddr_axi_arprot_), // output, width = 3, .arprot + .ddr_axi_arlen (_connected_to_ddr_axi_arlen_), // output, width = 8, .arlen + .ddr_axi_arready (_connected_to_ddr_axi_arready_), // input, width = 1, .arready + .ddr_axi_arsize (_connected_to_ddr_axi_arsize_), // output, width = 3, .arsize + .ddr_axi_arburst (_connected_to_ddr_axi_arburst_), // output, width = 2, .arburst + .ddr_axi_rvalid (_connected_to_ddr_axi_rvalid_), // input, width = 1, .rvalid + .ddr_axi_rready (_connected_to_ddr_axi_rready_), // output, width = 1, .rready + .ddr_axi_wvalid (_connected_to_ddr_axi_wvalid_), // output, width = 1, .wvalid + .ddr_axi_wlast (_connected_to_ddr_axi_wlast_), // output, width = 1, .wlast + .ddr_axi_wready (_connected_to_ddr_axi_wready_), // input, width = 1, .wready + .ddr_axi_bvalid (_connected_to_ddr_axi_bvalid_), // input, width = 1, .bvalid + .ddr_axi_bready (_connected_to_ddr_axi_bready_), // output, width = 1, .bready + .ddr_axi_awaddr (_connected_to_ddr_axi_awaddr_), // output, width = 32, .awaddr + .ddr_axi_awid (_connected_to_ddr_axi_awid_), // output, width = 2, .awid + .ddr_axi_araddr (_connected_to_ddr_axi_araddr_), // output, width = 32, .araddr + .ddr_axi_arid (_connected_to_ddr_axi_arid_), // output, width = 2, .arid + .ddr_axi_rdata (_connected_to_ddr_axi_rdata_), // input, width = 512, .rdata + .ddr_axi_rid (_connected_to_ddr_axi_rid_), // input, width = 2, .rid + .ddr_axi_wdata (_connected_to_ddr_axi_wdata_), // output, width = 512, .wdata + .ddr_axi_wstrb (_connected_to_ddr_axi_wstrb_), // output, width = 64, .wstrb + .ddr_axi_bid (_connected_to_ddr_axi_bid_), // input, width = 2, .bid + .irq_level (_connected_to_irq_level_) // output, width = 1, irq_level.irq + ); + |