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// Copyright 2020-2023 Intel Corporation.
//
// This software and the related documents are Intel copyrighted materials,
// and your use of them is governed by the express license under which they
// were provided to you ("License"). Unless the License provides otherwise,
// you may not use, modify, copy, publish, distribute, disclose or transmit
// this software or the related documents without Intel's prior written
// permission.
//
// This software and the related documents are provided as is, with no express
// or implied warranties, other than those that are expressly stated in the
// License.
/*
* Module `dla_aux_depthwise_debug`
*
* Debug functionality of the auxiliary block.
*
* WARNING! ONLY EDIT THE PARTS MARKED IN BETWEEN
* "START EDITING" AND "END EDITING"
*
* See README.md of the Example Aux block for more details.
*/
`undefineall
`resetall
`default_nettype none
module dla_aux_depthwise_debug
import dla_aux_depthwise_pkg::*;
#(
parameter aux_depthwise_arch_params_t ARCH // Architecture parameters
) (
input wire clk , // Clock
input wire i_resetn , // Active-low sync reset
//
input debug_config_t i_config , // Debug from config
input debug_group_t i_group , // Debug from group
//
input var logic [ARCH.DEBUG_AXI_PARAMS.ADDR_WIDTH-1:0] i_raddr , // Debug AXI read-address port
input var logic i_raddr_valid, // Debug AXI read-address port valid
output generic_response_t o_raddr , // Debug AXI read-address port response
input generic_response_t i_rdata , // Debug AXI read-data port response
output logic [ARCH.DEBUG_AXI_PARAMS.DATA_WIDTH-1:0] o_rdata , // Debug AXI read-data port
output logic o_rdata_valid // Debug AXI read-data port valid
);
// ------------------------------ START EDITING ------------------------------
// Limitation: Debug is to be implemented yet.
// ------------------------------ END EDITING ------------------------------
endmodule
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