1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
|
// Copyright 2021-2021 Intel Corporation.
//
// This software and the related documents are Intel copyrighted materials,
// and your use of them is governed by the express license under which they
// were provided to you ("License"). Unless the License provides otherwise,
// you may not use, modify, copy, publish, distribute, disclose or transmit
// this software or the related documents without Intel's prior written
// permission.
//
// This software and the related documents are provided as is, with no express
// or implied warranties, other than those that are expressly stated in the
// License.
`undefineall
// Port structure from config to control
interface depthwise_config_to_control_if #(
dla_aux_depthwise_pkg::aux_special_params_t special_params,
dla_interface_pkg::aux_data_pack_params_t data_pack_params,
int DIM1 = 1,
int DIM2 = 1
);
// ------------------------------ START EDITING ------------------------------
localparam TILE_COUNT = data_pack_params.GROUP_SIZE * data_pack_params.GROUP_NUM;
localparam CONFIG_ID_BITS = special_params.CONFIG_ID_WIDTH ;
localparam WINDOW_BITS_VERTICAL = $clog2(special_params.MAX_WINDOW_HEIGHT + 1);
localparam WINDOW_BITS_HORIZONTAL = $clog2(special_params.MAX_WINDOW_WIDTH + 1);
localparam STRIDE_BITS_VERTICAL = $clog2(special_params.MAX_STRIDE_VERTICAL + 1);
localparam STRIDE_BITS_HORIZONTAL = $clog2(special_params.MAX_STRIDE_HORIZONTAL + 1);
localparam TILE_BITS_VERTICAL = $clog2(special_params.MAX_TILE_HEIGHT + 1);
localparam TILE_BITS_HORIZONTAL = $clog2(special_params.MAX_TILE_WIDTH + 1);
localparam TILE_BITS_DEPTHWISE = $clog2(special_params.MAX_TILE_CHANNELS + 1);
localparam VERTICAL_DILATION_BITS_DEPTHWISE = $clog2(special_params.MAX_DILATION_VERTICAL + 1);
localparam HORIZONTAL_DILATION_BITS_DEPTHWISE = $clog2(special_params.MAX_DILATION_HORIZONTAL + 1);
localparam ELEMENT_BITS = data_pack_params.ELEMENT_BITS ;
// ------------------------------ END EDITING ------------------------------
typedef struct packed {
// ------------------------------ START EDITING ------------------------------
logic configured ;
//
logic padding_ignore ;
logic [ 1:0] padding_mode ;
logic [ ELEMENT_BITS-1:0] padding_constant ;
logic [ HORIZONTAL_DILATION_BITS_DEPTHWISE-1:0] dilation_horizontal ;
logic [ VERTICAL_DILATION_BITS_DEPTHWISE-1:0] dilation_vertical ;
logic [TILE_COUNT-1:0] [ TILE_BITS_HORIZONTAL-1:0] tile_horizontal_end ;
logic [TILE_COUNT-1:0] [ TILE_BITS_HORIZONTAL-1:0] tile_horizontal_start;
logic [TILE_COUNT-1:0] [ TILE_BITS_VERTICAL-1:0] tile_vertical_end ;
logic [TILE_COUNT-1:0] [ TILE_BITS_VERTICAL-1:0] tile_vertical_start ;
logic [ TILE_BITS_DEPTHWISE-1:0] tile_channels ;
logic [ TILE_BITS_HORIZONTAL-1:0] tile_width ;
logic [ TILE_BITS_VERTICAL-1:0] tile_height ;
logic [STRIDE_BITS_HORIZONTAL-1:0] stride_horizontal ;
logic [ STRIDE_BITS_VERTICAL-1:0] stride_vertical ;
logic [WINDOW_BITS_HORIZONTAL-1:0] window_width ;
logic [ WINDOW_BITS_VERTICAL-1:0] window_height ;
logic [ CONFIG_ID_BITS-1:0] config_id ;
// ------------------------------ END EDITING ------------------------------
} Type;
Type data [DIM1][DIM2];
modport sender (output data);
modport receiver (input data);
endinterface
// Port structure from control to lane(s)
interface depthwise_control_to_lane_if #(
dla_aux_depthwise_pkg::aux_special_params_t special_params,
dla_interface_pkg::aux_data_pack_params_t data_pack_params,
int DIM1 = 1,
int DIM2 = 1
);
localparam TILE_COUNT = data_pack_params.GROUP_SIZE * data_pack_params.GROUP_NUM;
localparam WINDOW_BITS_VERTICAL = $clog2(special_params.MAX_WINDOW_HEIGHT + 1);
localparam WINDOW_BITS_HORIZONTAL = $clog2(special_params.MAX_WINDOW_WIDTH + 1);
localparam MAX_WINDOW_HEIGHT = special_params.MAX_WINDOW_HEIGHT ;
localparam MAX_WINDOW_WIDTH = special_params.MAX_WINDOW_WIDTH ;
localparam MAX_DILATION_VERTICAL = special_params.MAX_DILATION_VERTICAL ;
localparam MAX_DILATION_HORIZONTAL = special_params.MAX_DILATION_HORIZONTAL ;
localparam VERTICAL_DILATION_BITS_DEPTHWISE = $clog2(special_params.MAX_DILATION_VERTICAL + 1);
localparam HORIZONTAL_DILATION_BITS_DEPTHWISE = $clog2(special_params.MAX_DILATION_HORIZONTAL + 1);
localparam VERTICAL_LINES = MAX_WINDOW_HEIGHT + ((MAX_WINDOW_HEIGHT-1) * (MAX_DILATION_VERTICAL-1));
typedef struct packed {
// only the handshake signal 'ready' is fixed in this structure, which is used by control to
// signal that the core is not stalled
logic ready;
// ------------------------------ START EDITING ------------------------------
logic line_buff_flush;
logic line_buff_wait_fill;
logic is_padding_zone_vert;
logic is_padding_zone_horiz;
logic [TILE_COUNT-1:0] [VERTICAL_LINES-1:0] en_pad_nan_vert ;
logic [TILE_COUNT-1:0] [VERTICAL_LINES-1:0] en_pad_zero_vert ;
logic [TILE_COUNT-1:0] [special_params.MAX_WINDOW_WIDTH -1:0] en_pad_nan_horiz ;
logic [TILE_COUNT-1:0] [special_params.MAX_WINDOW_WIDTH -1:0] en_pad_zero_horiz;
logic stride_valid;
logic [WINDOW_BITS_HORIZONTAL-1:0] window_width ;
logic [ WINDOW_BITS_VERTICAL-1:0] window_height ;
logic done; // Indicates that a depthwise_k_vec chunk of data is out
// We need these signals to keep track of when we switch layes because the filter bias
// cache will only be ready when in a new layer
logic configured_starting;
logic configured_ending;
logic [VERTICAL_DILATION_BITS_DEPTHWISE-1:0] dilation_vertical;
logic [HORIZONTAL_DILATION_BITS_DEPTHWISE-1:0] dilation_horizontal;
// ------------------------------ END EDITING ------------------------------
} Type;
Type data [DIM1][DIM2];
modport sender (output data);
modport receiver (input data);
endinterface
|
