diff options
Diffstat (limited to 'python/openvino/demo/ip/intel_ai_ip/verilog/dla_lt_mux.sv')
| -rw-r--r-- | python/openvino/demo/ip/intel_ai_ip/verilog/dla_lt_mux.sv | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/python/openvino/demo/ip/intel_ai_ip/verilog/dla_lt_mux.sv b/python/openvino/demo/ip/intel_ai_ip/verilog/dla_lt_mux.sv new file mode 100644 index 0000000..92b16a7 --- /dev/null +++ b/python/openvino/demo/ip/intel_ai_ip/verilog/dla_lt_mux.sv @@ -0,0 +1,38 @@ +// Copyright 2020-2022 Intel Corporation. +// +// This software and the related documents are Intel copyrighted materials, +// and your use of them is governed by the express license under which they +// were provided to you ("License"). Unless the License provides otherwise, +// you may not use, modify, copy, publish, distribute, disclose or transmit +// this software or the related documents without Intel's prior written +// permission. +// +// This software and the related documents are provided as is, with no express +// or implied warranties, other than those that are expressly stated in the +// License. + +`resetall +`undefineall +`default_nettype none + +module dla_lt_mux #( + parameter int VALUE_WIDTH, + parameter int NOUTPUT, + parameter int SELECT_WIDTH=$clog2(NOUTPUT) + ) ( + input wire i_valid, + input wire [SELECT_WIDTH:0] i_select, + input wire [VALUE_WIDTH-1:0] i_value, + output logic [VALUE_WIDTH-1:0] o_mux_output [NOUTPUT-1:0] +); + + always_comb + begin + o_mux_output <= '{default: '0}; + if (i_valid) + begin + o_mux_output[i_select] <= i_value; + end + end + +endmodule |